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| keesj | hmm https://github.com/quartiq/bscan_spi_bitstreams perhaps? | 07:13 |
|---|---|---|
| tpb | Title: GitHub - quartiq/bscan_spi_bitstreams (at github.com) | 07:13 |
| keesj | lite-scope also support the sr format | 07:53 |
| keesj | if anyone can have a look at my code here it would be much appreciated http://paste.ubuntu.com/p/vYvXKc4zdx/ I had troubles with configuring the serdes for my project and started on a simpler use case, a logic analyzer running at 800 Mhz. | 08:23 |
| tpb | Title: Ubuntu Pastebin (at paste.ubuntu.com) | 08:23 |
| keesj | I am feeding it a 50Mhz clock but when I look at the output traces it always looks pretty muche like the values are not chaning | 08:24 |
| keesj | e.g. https://i.imgur.com/YxMTpSt.png | 08:24 |
| _florent__ | keesj: is your 50Mhz clock synchronous to the FPGA clock? | 08:34 |
| keesj | no, it is async | 08:34 |
| keesj | I ... messed up the analyzer dump code.. /me wrong.. I have been looking at this for hours and it is only when I talk about is that I find the problem | 08:35 |
| keesj | much better https://i.imgur.com/tPNdMM2.png | 08:36 |
| _florent__ | it's seems better yes :) | 08:37 |
| keesj | nice.. now I and make my modifucations again and perhaps even "upstream" this as example | 08:37 |
| keesj | I was (and will continue) messing around the dump/common.py to convert this back to something that a logic analyzer can use (pulseview/sigrok) | 08:38 |
| _florent__ | for info, mithro has started integrating it with pulseview/sigrok: https://github.com/enjoy-digital/litescope/issues/8 | 08:40 |
| tpb | Title: Support pulseview / sigrok directly · Issue #8 · enjoy-digital/litescope · GitHub (at github.com) | 08:40 |
| keesj | I will have a look .. streaming and lre on the arty would be nice (using ehternet perhaps) | 08:41 |
| keesj | hmm I think the bug was in the original code but got "masked" the add_from_layout used the variable "i" that is set to 0 and gets increased at lines 72 | 08:43 |
| keesj | but https://github.com/enjoy-digital/litescope/blob/master/litescope/software/dump/common.py#L70 also uses the i variable in the for i in bla) | 08:44 |
| tpb | Title: litescope/common.py at master · enjoy-digital/litescope · GitHub (at github.com) | 08:44 |
| keesj | can those variable "interact"? | 08:44 |
| keesj | well values[i//2] is the "i" from the for i in range .. so i is masked there | 08:46 |
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| _florent__ | keesj: thanks, i just changed it | 10:51 |
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| keesj | if you are always so fast how can I ever contribute | 11:38 |
| keesj | thanks for being so pro active! | 11:41 |
| keesj | I am getting there https://i.imgur.com/wEbtDOQ.png but not quite yet. there is still something wrong somewhere (the upper is 48 Mhz the lower 24 Mhz) at 27ps the "slow" 24 Mhz signal goes high and d1[0] and d1[1] are "1" the cylcle after that d1[0] to d1[4] are 1 but the remaning d1[7:5] are 0 , I would not expect this in a 8x setup. | 11:51 |
| keesj | some aliasing is occuring | 12:50 |
| _florent__ | keesj: ah sorry, it was to avoid bothering you with a pull request, i'll let you create a pull request next time | 12:58 |
| keesj | thanks \o/ | 13:00 |
| keesj | it works now.. much better when you don't enable subsampling! | 13:59 |
| keesj | but .. at full speed with 4096 data points I can not even capture a single byte sent over rs232 :p | 15:11 |
| keesj | what does it take to move the data to ddr? gateware to setup ddr, and some kind of fifo? | 16:15 |
| _florent__ | if you use a SoC that is initializing the DRAM, you can create a new port on the DRAM controller with self.sdram.crossbar.get_port() | 17:28 |
| _florent__ | then you can use this port for a DMA: https://github.com/enjoy-digital/litedram/blob/master/litedram/frontend/dma.py | 17:29 |
| tpb | Title: litedram/dma.py at master · enjoy-digital/litedram · GitHub (at github.com) | 17:29 |
| _florent__ | you just have to provide a stream with address/data | 17:29 |
| keesj | I will do some more testing tomorrow and once that work try this approach | 19:39 |
| keesj | also sending data over the serial (at 115200 with the protocol overhead is not optimal). speeing this up would be nice ( to still have an easy way to connect) but mithro followed the ethernet route if I understand it correctly (also pretty cool) | 19:44 |
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| ambro718 | Hi. I am not able to access SPI flash through OpenOCD on Arty A7 100T. I think the problem is that the incorrect bscan_spi bitstream is used, from here: https://github.com/enjoy-digital/linux-on-litex-vexriscv/blob/master/prog/bscan_spi_xc7a35t.bit | 20:08 |
| tpb | Title: linux-on-litex-vexriscv/bscan_spi_xc7a35t.bit at master · enjoy-digital/linux-on-litex-vexriscv · GitHub (at github.com) | 20:08 |
| ambro718 | Where did this file come from, how can I get one for the correct FPGA? | 20:08 |
| ambro718 | _florent__: In https://github.com/enjoy-digital/litedram/commit/bc88cfa6f79d870690777da8097d1030f2086f50 you accidentally changed tWR instead of tRFC for MT16KTF1G64HZ | 20:13 |
| tpb | Title: modules: allow tRFC to be defined in ck or ns, fix some DDR3/DDR4 def… · enjoy-digital/litedram@bc88cfa · GitHub (at github.com) | 20:13 |
| _florent__ | ambro718: you can find the bscan_spi here: https://github.com/quartiq/bscan_spi_bitstreams | 20:40 |
| tpb | Title: GitHub - quartiq/bscan_spi_bitstreams (at github.com) | 20:40 |
| _florent__ | https://github.com/quartiq/bscan_spi_bitstreams/blob/master/bscan_spi_xc7a100t.bit | 20:41 |
| tpb | Title: bscan_spi_bitstreams/bscan_spi_xc7a100t.bit at master · quartiq/bscan_spi_bitstreams · GitHub (at github.com) | 20:41 |
| ambro718 | Thanks! | 20:41 |
| _florent__ | thanks for the MT16KTF1G64HZ, i'll fix it | 20:42 |
| _florent__ | ambro718: it's possible you'll have to change this line if it's not booting once flashed : https://github.com/enjoy-digital/linux-on-litex-vexriscv/blob/master/soc_linux.py#L59 | 20:45 |
| tpb | Title: linux-on-litex-vexriscv/soc_linux.py at master · enjoy-digital/linux-on-litex-vexriscv · GitHub (at github.com) | 20:45 |
| ambro718 | what's this? | 20:45 |
| _florent__ | ambro718: to verify the SPI flash is working correctly, you can exit the boot sequence escape/Q and type mr 0x20000000 128 | 20:45 |
| ambro718 | Ok I'll try. | 20:46 |
| _florent__ | and verify that you see the same hexdump than emulator.bin | 20:46 |
| _florent__ | it seems the new Arty boards are using different SPI flash than the previous one, so this parameter need to be adapted | 20:46 |
| _florent__ | Dolu had to do that but i don't remember which value was used | 20:47 |
| ambro718 | It seems to have frozen during flashing. https://paste.ubuntu.com/p/F9k7VcSWSP/ | 20:59 |
| tpb | Title: Ubuntu Pastebin (at paste.ubuntu.com) | 20:59 |
| ambro718 | Oh never mind, it's going on. | 20:59 |
| Dolu | _florent__ https://github.com/enjoy-digital/linux-on-litex-vexriscv/issues/15#issuecomment-493323867 => 7 | 21:04 |
| tpb | Title: Issue booting linux on ArtyA7 · Issue #15 · enjoy-digital/linux-on-litex-vexriscv · GitHub (at github.com) | 21:04 |
| _florent__ | Dolu: ok thanks | 21:05 |
| somlo | _florent: this line: https://github.com/enjoy-digital/litex/blob/master/litex/soc/integration/cpu_interface.py#L152 (and also line 186) both seem to be a recognition of the fact that CSR (sub-)register MMIO addresses are 32-bit aligned | 21:06 |
| tpb | Title: litex/cpu_interface.py at master · enjoy-digital/litex · GitHub (at github.com) | 21:06 |
| somlo | any chance you can point me to the place in the LiteX sources where that alignment is actually *specified* ? | 21:06 |
| ambro718 | I flashed the SPI but what do I check now? I did "lxterm /dev/ttyUSB1" and there is nothing, and pressing the reset button does nothing. | 21:13 |
| ambro718 | If I load FPGA bitstream manually then I get this: https://paste.ubuntu.com/p/gtVGG4J3jr/ | 21:16 |
| tpb | Title: Ubuntu Pastebin (at paste.ubuntu.com) | 21:16 |
| ambro718 | says it's loading stuff from flash but then hangs at "Liftoff" | 21:16 |
| _florent__ | somlo: it's probably here: https://github.com/enjoy-digital/litex/blob/master/litex/soc/interconnect/csr_bus.py#L146-L171 | 21:16 |
| tpb | Title: litex/csr_bus.py at master · enjoy-digital/litex · GitHub (at github.com) | 21:16 |
| _florent__ | ambro718: can you try pressing escape or Q before the boot sequence | 21:17 |
| _florent__ | and then do mr 0x20000000 128 and report your results here | 21:17 |
| _florent__ | (it should be similar to emulator.bin hexdump) | 21:18 |
| ambro718 | https://paste.ubuntu.com/p/hVmbP2H5qg/ | 21:20 |
| tpb | Title: Ubuntu Pastebin (at paste.ubuntu.com) | 21:20 |
| ambro718 | Seems "similar" but I can't quite match it. | 21:20 |
| ambro718 | well the first two bytes from the file (6f 00) are not in the flash | 21:23 |
| _florent__ | ok, so that's the same problem than https://github.com/enjoy-digital/linux-on-litex-vexriscv/issues/15#issuecomment-493323867 | 21:25 |
| tpb | Title: Issue booting linux on ArtyA7 · Issue #15 · enjoy-digital/linux-on-litex-vexriscv · GitHub (at github.com) | 21:25 |
| _florent__ | you can change this to 7: https://github.com/enjoy-digital/linux-on-litex-vexriscv/blob/master/soc_linux.py#L59 | 21:26 |
| tpb | Title: linux-on-litex-vexriscv/soc_linux.py at master · enjoy-digital/linux-on-litex-vexriscv · GitHub (at github.com) | 21:26 |
| ambro718 | Okay, I'll try 7 and then 15 if that doesn't work | 21:31 |
| ambro718 | 7 did it, it booted Linux once I loaded new firmware :) | 21:40 |
| ambro718 | So how would one support board variants in litex / linux-on-litex-vexriscv ? | 22:12 |
| ambro718 | I want to add support for Arty A7 100T but I'm not sure where it could fit. | 22:12 |
| ambro718 | I suppose in the end it should be possible to just say "./make.py --board=arty100t" | 22:13 |
| ambro718 | but it's more complicated with random variants like different RAM chip and different SPI flash | 22:14 |
| ambro718 | Maybe extensions in the board name like "arty100t+flash:xxx+ram:yyy"? | 22:17 |
| ambro718 | since part numbers are big we could just enumerate the known possibilities (xxx=1,2,...) and document them somewhere | 22:19 |
| ambro718 | an alternative is to make the user write a trivial .py file defining a board variant | 22:20 |
| Dolu | Do not forget BR2_PACKAGE_SL=y , that's very important | 23:21 |
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| Dolu | Ahh also, | 23:37 |
| Dolu | I tested loading the images via the CPU JTAG, and that's fine. At 10 MHZ JTAG, it load at 170 KB/s | 23:38 |
| Dolu | Using openocd with its load_image do the work. | 23:39 |
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