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| key2 | what do you guys think about that: i generate a ROM for my usb HS core using kconfig https://asciinema.org/a/fxz8ACzb4yYQ3C42VcWvbLuQq | 12:08 |
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| tpb | Title: untitled - asciinema (at asciinema.org) | 12:08 |
| keesj | I think it is kinda interesting. do you parse the .config afterward in your python code? | 15:40 |
| keesj | I like that litex is mostly python but having done kconfig type stuff before I also see some potential. was it much work compared to creating a python structure? | 15:41 |
| _florent__ | key2: thanks for sharing, that's nice. Being able to configure the cores with kconfig could also be useful to ease custom cores generation/integration when used with OSes. | 17:40 |
| key2 | well in this case, I generate a config.h | 17:41 |
| key2 | which then gets compiled and generate the ROM | 17:41 |
| key2 | as well as generates a python file for migen | 17:41 |
| key2 | I guess I should have shown the process more deeply | 17:41 |
| _florent__ | feel free to share more :) | 17:41 |
| key2 | well once compiled it generates a file like this | 17:53 |
| key2 | https://www.irccloud.com/pastebin/OSIlwpbB/ | 17:53 |
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 17:53 |
| key2 | which is used by the EP0 controller in order to answer the request the host send | 17:54 |
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| ambro718 | Hi. I'm interested in this line that controls the memory clock rate: https://github.com/enjoy-digital/litex/blob/master/litex/boards/targets/arty.py#L66 | 18:27 |
| tpb | Title: litex/arty.py at master · enjoy-digital/litex · GitHub (at github.com) | 18:27 |
| ambro718 | This defines the ratio between sys_clk_freq and the memory frequency, or data rate? | 18:28 |
| ambro718 | so if sys_clk_freq is 100 MHz, is the memory clock frequency 400 MHz or 200 MHz? | 18:28 |
| ambro718 | My experience with Vivado is that 1:4 means the frequency of the logic clock (sys_clk_freq) is 1/4 the frequency of the memory clock. | 18:30 |
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| _florent__ | ambro718: your understanding is correct. This ratio has to be defined for the SDRAM module (to compute correct timings), but also for the PHY: | 20:23 |
| _florent__ | https://github.com/enjoy-digital/litedram/blob/master/litedram/phy/s7ddrphy.py#L49 | 20:23 |
| tpb | Title: litedram/s7ddrphy.py at master · enjoy-digital/litedram · GitHub (at github.com) | 20:23 |
| _florent__ | nphases | 20:23 |
| _florent__ | But S7DDRPHY currently only supports DDR3 with 1:4 ratio, DDR2 with 1:2 ratio | 20:24 |
| ambro718 | _florent__: so with this Arty code, with 100 MHz sys_clk_freq, we get 400 MHz clock period for the clop and 800 MHz per-pin data rate? | 20:24 |
| ambro718 | * for the chip | 20:25 |
| _florent__ | yes that's correct | 20:26 |
| ambro718 | _florent__: Well then I see two problems. First is that we are running the RAM too fast for the Arty board.https://reference.digilentinc.com/reference/programmable-logic/arty-a7/reference-manual | 20:27 |
| tpb | Title: Arty A7 Reference Manual [Reference.Digilentinc] (at reference.digilentinc.com) | 20:27 |
| ambro718 | Max. clock period 3000ps (667Mbps data rate) | 20:27 |
| ambro718 | _florent__: second is that the ck_to_cycles is written like the ratio was the ratio between the system clock and ram clock frequency, when CK actually means one clock edge. https://github.com/enjoy-digital/litedram/blob/master/litedram/modules.py#L80 | 20:29 |
| tpb | Title: litedram/modules.py at master · enjoy-digital/litedram · GitHub (at github.com) | 20:29 |
| ambro718 | My understanding is that CK in data sheets means one clock edge (half clock period), so with 1:4 ratio we need to multiply by 8 to get from CK to system clocks. | 20:31 |
| ambro718 | Here's the data sheet for the RAM chip on my Arty board (which is actually a different chip than the reference says): http://www.issi.com/WW/pdf/43-46TR16128B-82560BL.pdf | 20:32 |
| ambro718 | Somewhere this is hidden: "Unit “nCK” represents one clock cycle of the input clock, counting the actual clock edges". | 20:34 |
| ambro718 | and the nCK values of the timings are in the right order of magnitude (I believe nCK here is what CK is supposed to mean in this code) | 20:35 |
| ambro718 | Am I making any sense? | 20:42 |
| _florent__ | ambro718: i'm not able to look at that now, but will do tomorrow, i'll answer here is you are still connected | 20:54 |
| ambro718 | Ok great, thanks, I'll come come back here tomorror at around the same time. | 20:54 |
| ambro718 | Huh, maybe nCK does actually mean a full clock cycle. It's hard to find it explained in a clear way. | 21:06 |
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