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| sb0 | _florent__: do you have a ZC706? | 06:03 |
|---|---|---|
| _florent__ | sb0: no i don't have this one | 07:06 |
| keesj | _florent__: I am reading your comment to use a converter (to convert my 4 bits serdes signal to a serial stream) https://paste.ubuntu.com/p/BdFRvdjDf3/ but I remain clueless. I think that what I need to do is to "speed" up the scope to provide 4 samples per cycle then I can match my serdes inputs to the samples | 07:20 |
| tpb | Title: Ubuntu Pastebin (at paste.ubuntu.com) | 07:20 |
| keesj | possibly the SubSampler has something to do with it | 07:24 |
| _florent__ | keesj: from what i remember, you want to concatenate the data outputed by the ISERDESE2 to form a stream with a larger data-width? | 07:24 |
| keesj | I want to represent my serial stream as serial stream | 07:26 |
| keesj | from 1 bit input -> 4 bits serdes -> 1 bit output for the logic analyzer | 07:27 |
| keesj | I think I need to modify around here https://github.com/enjoy-digital/litescope/blob/master/litescope/core.py#L264 | 07:29 |
| tpb | Title: litescope/core.py at master · enjoy-digital/litescope · GitHub (at github.com) | 07:29 |
| keesj | the storage should create 4 "samples" v.s. the 4 bits sample | 07:29 |
| _florent__ | keesj: but here we are using serdes because the frequency is too high for the FPGA fabric, so that's not possible to have your data as a 1-bit data stream in the FPGA fabric | 07:29 |
| _florent__ | keesj: if you want to do a modification, you'll need to do it in the software | 07:30 |
| keesj | I kinda know that ( and I am fine for the "real" world to be like this) but I still should be able to view this data using litescope as if it was serial | 07:31 |
| keesj | on the host side you mean? | 07:32 |
| _florent__ | yes on the host | 07:32 |
| _florent__ | maybe use the capability to export the dump in python, then do the adaptation on this and reimport the modified dump, then export to a vcd with litescope software | 07:34 |
| keesj | I do not sea a reason why this would not work e.g. instead of a 1 bit clock domain create a 4 bit clock .. somewhere around here https://github.com/enjoy-digital/litescope/blob/master/litescope/core.py#L172 | 07:36 |
| tpb | Title: litescope/core.py at master · enjoy-digital/litescope · GitHub (at github.com) | 07:36 |
| keesj | of course (indeed) I can do it in software | 07:37 |
| keesj | 2 bit clock (not 4) | 07:38 |
| _florent__ | i'm not sure to understand what you want to change in the gateware | 07:39 |
| _florent__ | if you do a 1-bit serial stream in the gateware, the frequency will be too high, so you need to stay with the 4-bit serial stream in the gateware | 07:39 |
| keesj | I Want to store the 4 bits I get every clock cycle to separate sample memory locations. I don't need the 1 bit stream indeed just to store it in the buffer like that | 07:44 |
| keesj | every clock cycle store bit[0] of the serdes to memory location[0] ,, bit one to location[1] etc also advance the "scope" of 4 samples | 07:46 |
| keesj | I think I understand better know what I want. I will try making an example | 07:51 |
| _florent__ | thanks, an example will help me understand what you want to achieve | 07:56 |
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