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| keesj | I have an error I do not quite understand https://paste.ubuntu.com/p/DYwxpZDThk/ | 08:52 |
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| tpb | Title: Ubuntu Pastebin (at paste.ubuntu.com) | 08:52 |
| keesj | after (way to long) i discovered my signal are not sstl135 but 1.8v (hence I was not seeing the low values.... | 08:53 |
| keesj | Now I am trying to use SSTL18 (I II I_DCI II_DCI) to see where it goes but somehow xilinx thinks differently about what I am asking | 08:53 |
| keesj | specifying SSTL18_I does "fix" the problem in terms of warning. | 08:56 |
| keesj | rubber ducking herer .. but the reason is that not all IO standards are available on all ports (SelectIO give better information on this as there is a table with the compatible ports) | 09:06 |
| keesj | soo. doing a typo in the IOSTANDARD fails to late | 09:07 |
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| _florent__ | keesj: yes, this kind of errors are reported late in the build... | 11:27 |
| keesj | I lowered the ddr speed (to 400 MHz) improved the grounding | 11:42 |
| keesj | the signals remain high but when I ground them still they remain high about 1/2 of the time | 11:43 |
| keesj | yestedey it looked like this https://i.imgur.com/OWmh0Nz.png | 11:43 |
| keesj | when I ground it looks like https://i.imgur.com/luJTech.png (the two upper lines) | 11:45 |
| keesj | are "grounded" but is still looks like $RANDOM stuff horrible | 11:46 |
| keesj | now it looks like https://i.imgur.com/CCCWKxj.png | 11:47 |
| keesj | (this is clocks + nwe) the clock look crap but at least the voltage on the NWE is low enough | 11:48 |
| keesj | let me make a niver measurement | 11:49 |
| keesj | https://i.imgur.com/Zpcnaw2.png | 11:53 |
| somlo | is there some way (in LiteX, or the underlying migen) to have $display statements added to the generated verilog code matching some specific place in the Python (e.g., in a FSM)? | 13:38 |
| _florent__ | yes, you can use use Display | 13:41 |
| somlo | is that a migen thing, then? Only two instances in the litex code base, none of them something I can immitate :) | 13:42 |
| somlo | ^ looking for an example of how to use it, or where to RTFM on the syntax | 13:45 |
| somlo | hmm, I see there's a few examples in litesdcard/sim/sim.py | 13:51 |
| _florent__ | somlo it's very similar to printf | 14:02 |
| somlo | _florent__: thanks, makes sense :) the litesdcard examples only show hardcoded strings, but I can imagine if it's getting translated into verilog $display it can probably accept %h and %b and friends as well... | 14:03 |
| _florent__ | you can use it like that: https://github.com/enjoy-digital/linux-on-litex-vexriscv/commit/02a8b74e839eb8b72486a43d529dce20b1e43cbd | 14:03 |
| tpb | Title: sim: add debug traces on periphs accesses · enjoy-digital/linux-on-litex-vexriscv@02a8b74 · GitHub (at github.com) | 14:03 |
| somlo | thanks, looks reasonable and straightforward :) | 14:05 |
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| somlo | apparently, Display(...) doesn't work from inside an fsm.act(...) | 17:17 |
| somlo | ... unless I'm doing something subtly wrong... | 17:17 |
| _florent__ | ah yes, possible | 17:18 |
| _florent__ | you can workaround it with: | 17:19 |
| _florent__ | display = Signal() | 17:19 |
| _florent__ | set display.eq(1) inside the FSM | 17:19 |
| _florent__ | (where you want to display things) | 17:19 |
| _florent__ | then add a self.sync += If(display, Display("...")) | 17:19 |
| somlo | and then write a self.sync where I display e.g. fsm.decoding[fsm.state] and the like | 17:20 |
| somlo | ok, trying that now | 17:20 |
| somlo | I'd also have figure out when to set display.eq(0) or else it'll just stay set, right? | 17:22 |
| somlo | assuming it gets implemented as a register/flipflop | 17:23 |
| somlo | or, maybe I need to understand and use NextValue(display, X), to get it set only when appropriate... | 17:26 |
| _florent__ | you just need to set display.eq(1), it will automatically be 0 (reset value) in the others cases | 17:30 |
| somlo | that should make it easier, then -- thanks! :) | 17:30 |
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