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| futarisIRCcloud | So, I've got a ~1.2GB ext4 core-image-lsb-sdk rv32ima rootfs that I built using meta-riscv / openembedded... I guess I'll need to fix up the network driver / NFS or get litesdcard running in arty linux to test it on hardware. | 05:54 |
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| keesj | the ClockDomain() code remains magic to me | 08:13 |
| keesj | how do I know the name of the clock ? | 08:13 |
| _florent__ | keesj: by default the clock domain is "sys" | 08:14 |
| _florent__ | by when you do something like this: self.clock_domaines.cd_foo = ClockDomain(), your clock domain will be called "foo" | 08:15 |
| keesj | my code currently looks like this http://paste.ubuntu.com/p/PWWGywGfCn/ | 08:15 |
| tpb | Title: Ubuntu Pastebin (at paste.ubuntu.com) | 08:15 |
| keesj | self.clock_domains.cd_sys = ClockDomain() defines the "sys" clock? | 08:16 |
| _florent__ | ok so you have two clocks domain: sys and por | 08:17 |
| keesj | and I want to define a sys2x clock (the clk_bufio) | 08:17 |
| _florent__ | you can just see clock domain as an object that encapsulate the clk and reset | 08:17 |
| keesj | because at line 85 ish I want to use sys and sys2x | 08:18 |
| _florent__ | ok, then in your CRG, you need to create the sys2s clock domain | 08:19 |
| keesj | so .. line 86 becomes .. ClockSignal("sys") ? | 08:19 |
| _florent__ | yes | 08:20 |
| keesj | Ok .. I will try that | 08:20 |
| _florent__ | and if in the CRG you connect clk_bufio to self.cd_sys2x.clk, line85 you can use ClockSignal("sys2x") | 08:21 |
| keesj | like this http://paste.ubuntu.com/p/JPDKcj4D7N/ | 08:26 |
| tpb | Title: Ubuntu Pastebin (at paste.ubuntu.com) | 08:26 |
| keesj | it does compile :P | 08:27 |
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| _florent__ | futarisIRCcloud: i merged you ULX3S support and tested on hardware: https://github.com/enjoy-digital/linux-on-litex-vexriscv/issues/5 | 08:39 |
| tpb | Title: finish ULX3S support · Issue #5 · enjoy-digital/linux-on-litex-vexriscv · GitHub (at github.com) | 08:39 |
| _florent__ | futarisIRCcloud: it's almost working, but the issue is not related to the board but with the actual minimum memory requirement: | 08:40 |
| _florent__ | daveshah: can i merge your 2 dev branches? (linux_liteeth, buildroot_tweaks) | 08:50 |
| daveshah | Go ahead | 08:51 |
| _florent__ | ok thanks | 08:52 |
| daveshah | buildroot_tweaks is just some random niceties | 08:52 |
| futarisIRCcloud | Ok. What does the kernel log say? | 08:52 |
| daveshah | liteeth stuff needs the interrupt stuff fixed, which I probably won't have time to do this week so feel free to take that | 08:52 |
| _florent__ | futarisIRCcloud: the kernel log is here: https://github.com/enjoy-digital/linux-on-litex-vexriscv/issues/5 | 08:59 |
| tpb | Title: finish ULX3S support · Issue #5 · enjoy-digital/linux-on-litex-vexriscv · GitHub (at github.com) | 08:59 |
| Dolu | This is probably the issue : https://github.com/enjoy-digital/linux-on-litex-vexriscv/blob/7ab77c974f8af07dfa13531e87d65d5f9cd5834d/buildroot/board/litex_vexriscv/litex_vexriscv.dts#L63 | 09:00 |
| tpb | Title: linux-on-litex-vexriscv/litex_vexriscv.dts at 7ab77c974f8af07dfa13531e87d65d5f9cd5834d · enjoy-digital/linux-on-litex-vexriscv · GitHub (at github.com) | 09:00 |
| Dolu | At least, part of it | 09:00 |
| _florent__ | daveshah: yes i'll see if i can do that this week, for now i'm just trying to list the things to do | 09:00 |
| _florent__ | Dolu: ah yes, that could explain things :) | 09:00 |
| futarisIRCcloud | mithro: minispartan6+ with Spartan 6 LX 25 should be able to run HDMI2USB in Linux. | 09:08 |
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| _florent__ | futarisIRCcloud: at least minispartan6 Spartan6 LX25 runs linux: https://hastebin.com/etapuqabon.cs :) | 11:23 |
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| keesj | is there a nice way to geneate the analyzer.csv and csr.csv? I currently "hacked" the methods together | 11:47 |
| keesj | https://paste.ubuntu.com/p/Bsbh4XZGrv/ something like this | 11:48 |
| tpb | Title: Ubuntu Pastebin (at paste.ubuntu.com) | 11:48 |
| keesj | and.. I do not feel confident about the soc.finalize() either | 11:50 |
| keesj | it works[tm] | 11:50 |
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| _florent__ | keesj: i'm usually generating it while building the SoC with Builder, there is no nice way to generate it otherwise for now. Your hack seems fine | 12:18 |
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| futarisIRCcloud | _florent__ / daveshah / Dolu1990 / mithro / somlo / tinyfpga_ / xobs: https://twitter.com/GregDavill/status/1125846094787690496 | 23:42 |
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