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somlo | _florent_: studying the AXI & Wishbone code in litex, I ended up wondering about https://github.com/enjoy-digital/litex/blob/b682dacdd70d3e8f5300487de7d7c487ccea2a1f/litex/soc/interconnect/axi.py#L81 | 18:52 |
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tpb | Title: litex/axi.py at b682dacdd70d3e8f5300487de7d7c487ccea2a1f · enjoy-digital/litex · GitHub (at github.com) | 18:52 |
somlo | it appears it's declared, and assigned to in the immediately following line, but then never used anywhere | 18:53 |
somlo | it also appears redundant with https://github.com/enjoy-digital/litex/blob/b682dacdd70d3e8f5300487de7d7c487ccea2a1f/litex/soc/interconnect/axi.py#L70 | 18:53 |
tpb | Title: litex/axi.py at b682dacdd70d3e8f5300487de7d7c487ccea2a1f · enjoy-digital/litex · GitHub (at github.com) | 18:53 |
somlo | which *does* get utilized inside the FSM | 18:53 |
somlo | so, are lines 81-82 dead code, or am I missing something? :) | 18:54 |
_florent_ | somlo: thanks, indeed that's dead code | 20:26 |
somlo | _florent_: also, shouldn't https://github.com/enjoy-digital/litex/blob/552b0243b398502d6140715139c1739227851b0f/litex/soc/interconnect/axi.py#L63 be "assert axi.data_width == len(wishbone.dat_r)" instead ? :) | 20:31 |
tpb | Title: litex/axi.py at 552b0243b398502d6140715139c1739227851b0f · enjoy-digital/litex · GitHub (at github.com) | 20:31 |
somlo | _florent_: https://github.com/enjoy-digital/litex/pull/156 | 20:51 |
tpb | Title: soc/interconnect/axi: address length cleanup by gsomlo · Pull Request #156 · enjoy-digital/litex · GitHub (at github.com) | 20:51 |
somlo | I'm guessing whether I'm right or wrong that's a better place to resolve it than here, IRC being a volatile medium and whatnot :) | 20:51 |
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