Wednesday, 2019-03-27

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somlo_florent_: studying the AXI & Wishbone code in litex, I ended up wondering about https://github.com/enjoy-digital/litex/blob/b682dacdd70d3e8f5300487de7d7c487ccea2a1f/litex/soc/interconnect/axi.py#L8118:52
tpbTitle: litex/axi.py at b682dacdd70d3e8f5300487de7d7c487ccea2a1f · enjoy-digital/litex · GitHub (at github.com)18:52
somloit appears it's declared, and assigned to in the immediately following line, but then never used anywhere18:53
somloit also appears redundant with https://github.com/enjoy-digital/litex/blob/b682dacdd70d3e8f5300487de7d7c487ccea2a1f/litex/soc/interconnect/axi.py#L7018:53
tpbTitle: litex/axi.py at b682dacdd70d3e8f5300487de7d7c487ccea2a1f · enjoy-digital/litex · GitHub (at github.com)18:53
somlowhich *does* get utilized inside the FSM18:53
somloso, are lines 81-82 dead code, or am I missing something? :)18:54
_florent_somlo: thanks, indeed that's dead code20:26
somlo_florent_: also, shouldn't https://github.com/enjoy-digital/litex/blob/552b0243b398502d6140715139c1739227851b0f/litex/soc/interconnect/axi.py#L63 be "assert axi.data_width    == len(wishbone.dat_r)" instead ? :)20:31
tpbTitle: litex/axi.py at 552b0243b398502d6140715139c1739227851b0f · enjoy-digital/litex · GitHub (at github.com)20:31
somlo_florent_: https://github.com/enjoy-digital/litex/pull/15620:51
tpbTitle: soc/interconnect/axi: address length cleanup by gsomlo · Pull Request #156 · enjoy-digital/litex · GitHub (at github.com)20:51
somloI'm guessing whether I'm right or wrong that's a better place to resolve it than here, IRC being a volatile medium and whatnot :)20:51

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