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| futarisIRCcloud | _florent_: Is the latest VexRiscV linux as per https://github.com/SpinalHDL/VexRiscv/issues/60#issuecomment-473519457 ? | 08:15 |
|---|---|---|
| tpb | Title: Linux on VexRiscv · Issue #60 · SpinalHDL/VexRiscv · GitHub (at github.com) | 08:15 |
| _florent_ | futarisIRCcloud: i haven't tested the latest changes myself yet, this is still very experimental, we now need to discuss and merge things cleanly | 11:05 |
| xobs | futarisIRCcloud: I've been playing with smaller Vex core for Fomu, so _florent_ added a way to manually override the verilog source for the cpu. It's super handy. | 12:08 |
| somlo | What would be the least painful way to add rocket-chip as one of the litex.soc.cores.cpu options? Out of the box, Rocket exposes AXI interfaces for RAM and MMIO -- could litex just use that, or would it make more sense to add direct wishbone support to rocket first? | 13:57 |
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| _florent_ | somlo: for the ram, you can have AXI port with LiteDRAM, for the MMIO, if it's not doing bursts you can use the AXI to Wishbone module: https://github.com/enjoy-digital/litex/blob/master/litex/soc/interconnect/axi.py#L59 | 14:46 |
| tpb | Title: litex/axi.py at master · enjoy-digital/litex · GitHub (at github.com) | 14:46 |
| somlo | so let's say I add a rocket folder to litex.soc.cores.cpu; there will be a "class Rocket(Module)" with an __init__ method | 16:02 |
| somlo | which will have to set self.ibus and self.dbus | 16:02 |
| somlo | will those have to be wishbone interfaces (so whatever the core's verilog exposes had better be translated to wishbone first) ? | 16:03 |
| somlo | so far all existing cores use wishbone, so I'm kinda assuming that to be the case (would love to be wrong though :) ) | 16:04 |
| _florent_ | somlo: the infrastructure is not handling AXI natively yet, so the easiest way for now if probably to provide a Rocket Module with wishbone bridge already integrated | 16:45 |
| _florent_ | this way, you'll be able to reuse this Module with the existing infrastructure | 16:45 |
| _florent_ | if you want to support AXI natively, you'll need to modify SoCCore/SoCSDRAM to handle that | 16:46 |
| _florent_ | i'm also planning to do it in the future, i'll be happy to help if you want to go that way | 16:47 |
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