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| acathla | Hi | 10:15 |
|---|---|---|
| xobs | Hi hi | 10:15 |
| acathla | I have a SoC with only a wishbone bridge with uart. It works with some basic CSR | 10:16 |
| acathla | I have a (migen) Memory module I would like to write to and read from the UART, what's the best way to do this? | 10:18 |
| acathla | I found a CSRMemoryRegion in the sources, but i'm not sure it does anything usefull, and there is no doc or example or comment as usual :( | 10:19 |
| _florent_ | acathla: you can use this: https://github.com/enjoy-digital/litex/blob/master/litex/soc/interconnect/wishbone.py#L630 | 10:22 |
| tpb | Title: litex/wishbone.py at master · enjoy-digital/litex · GitHub (at github.com) | 10:22 |
| _florent_ | you can define your wishbone memory like this: https://github.com/enjoy-digital/versa_ecp5/blob/master/versa_ecp5.py#L222 | 10:25 |
| tpb | Title: versa_ecp5/versa_ecp5.py at master · enjoy-digital/versa_ecp5 · GitHub (at github.com) | 10:25 |
| _florent_ | but instead of specifying the size of the SRAM, just pass your actual memory | 10:25 |
| _florent_ | you will also have to define your memory in mem_map | 10:26 |
| _florent_ | and register it | 10:26 |
| _florent_ | as done for firmware_ram in the link | 10:26 |
| xobs | Is there a recommended CPU to use with litex? I know it defaults to lm32, but is that still the preferred core? | 11:19 |
| acathla | _florent_, thank you, it does not work yet. What's the difference between SoCCore and SoCSDRAM? Your example uses SoCSDRAM but mine was not. | 11:28 |
| acathla | I have the same error with both : ...soc_core.py", line 206, in __init__ \\ self.register_mem("sram", self.mem_map["sram"], self.sram.bus, integrated_sram_size) \\ KeyError: 'sram' | 12:10 |
| xobs | acathla: from what I understand, SoCSDRAM includes external DDR, so it includes things like link training. | 12:24 |
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| acathla | xobs, ok, useless for my bare tinyfpga | 12:57 |
| keesj | you are playing on the tinyfpga ? | 13:07 |
| acathla | The _bx yes | 13:23 |
| _florent_ | xobs: lm32/mor1kx are working fine but i'm switching to vexriscv progressively | 14:04 |
| _florent_ | xobs: picor32 can be interesting for some specific cases, but vexrisc has better performances/resource usage and more configurations | 14:05 |
| xobs | _florent_: the question has to do more with the compilers that I target. I have a riscv toolchain that I've built for Raspberry Pi, and I'm wondering if I should take the effort to build an lm32 one. | 14:06 |
| _florent_ | if everything works fine with a riscv cpu for you, i would just use that | 14:07 |
| _florent_ | acathla: you need to add your sram to the mem_map, as it's done here for firmware_ram: https://github.com/enjoy-digital/versa_ecp5/blob/master/versa_ecp5.py#L205 | 14:09 |
| tpb | Title: versa_ecp5/versa_ecp5.py at master · enjoy-digital/versa_ecp5 · GitHub (at github.com) | 14:09 |
| _florent_ | acathla: SoCCore is fine for you | 14:09 |
| acathla | _florent_, it works now, but I have 2 sram regions, it seems there is one by default (litex/soc/integration/soc_core.py). | 14:19 |
| _florent_ | acathla: yes you can use another name | 14:20 |
| acathla | If I replace the sram_size by my Memory it does not work | 14:20 |
| _florent_ | acathla: and use 0x30000000 as the firmware_ram in the example | 14:20 |
| _florent_ | acathla: what's the error message? | 14:20 |
| acathla | many lines ending with "raise IndexError" | 14:21 |
| acathla | wishbone.py", line 655, in <listcomp> , for i in range(bus_data_width//8)] | 14:22 |
| acathla | _florent_, and my initialization is something like Memory(width, depth, init=data) | 14:23 |
| _florent_ | acathla: can you share your actual code? | 14:24 |
| acathla | My horrible code? hum | 14:24 |
| acathla | _florent_, I can also forget about my own Memory modules and use those sram with initialization | 14:29 |
| _florent_ | ah yes, you can also do that | 14:32 |
| acathla | _florent_, do you have an example of how to read and write to sram through uart-bridge? | 15:32 |
| acathla | I tried some "wb.write(wb.mems.s_ram,42)" but I have a AttributeError: 'CSRMemoryRegion' object has no attribute 'to_bytes' | 15:34 |
| _florent_ | wb.write(addr, value), wb.read(addr) :) | 15:34 |
| _florent_ | can you try wb.write(wb.mems.s_ram.base, 42)? | 15:34 |
| acathla | ah, right, I removed too much, it works ! | 15:40 |
| acathla | _florent_, but if I use a SRAM Module, the only way to access it is through the wishbone bus... | 16:20 |
| _florent_ | acathla: that's why you can choose if SRAM provide the memory or if you provide it | 16:21 |
| _florent_ | acathla: you should be able to pass the Memory you create outside to SRAM | 16:24 |
| acathla | I should... | 16:24 |
| acathla | I can also use big CSR | 16:25 |
| _florent_ | if you create a minimal design with the error, i'll look at that | 16:26 |
| acathla | Ok | 16:28 |
| acathla | https://sebsauvage.net/paste/?ad8921c6013e734c#Q4JhP+Srh59yUvPzA2CrRnvKqhx1x5L1M4OsGqNI/uw= | 16:51 |
| tpb | Title: ZeroBin (at sebsauvage.net) | 16:51 |
| acathla | _florent_, this code in targets/tinyfpga_bx/ will produce the same error as before | 16:51 |
| acathla | it just needs the standard base.py I think, may be I added some uart | 16:52 |
| _florent_ | the issue is that the width of your memory is 8 bits and SRAM expect 32 bits | 17:05 |
| acathla | Oh that's all, ok =) | 17:11 |
| acathla | Thank you | 17:12 |
| keesj | :q | 19:49 |
| keesj | oops | 19:49 |
| keesj | acathla: I don't have the from targets.utils import csr_map_update | 19:52 |
| keesj | I have litex/soc/integration/soc_core.py:def csr_map_update | 19:53 |
| keesj | xobs: building the lm gnu toolchain was suprizingly easy(on ubuntu) e.g. following https://github.com/enjoy-digital/litex/blob/master/README#L90 | 19:56 |
| tpb | Title: litex/README at master · enjoy-digital/litex · GitHub (at github.com) | 19:56 |
| keesj | there was no libc / syslib messing arround (so far) | 19:57 |
| keesj | I mean starting at line 108, not the conda method line 90 | 19:58 |
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