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| somlo | I tried to synthesize the litedram nexys4ddr example (using the generated litedram_core.tcl script, and the placer fails with "IO placement failed due to overutilization. This design contains 780 i/o ports while the target device: 7a100t package: csg324, contains only 210 available user I/O." | 13:14 |
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| somlo | this is vivado 2018.2, btw | 13:14 |
| daveshah | somlo: sounds like your top level module is wrong | 13:15 |
| somlo | I'm guessing maybe the axi ("user ports" in nexys4ddr_config.py") is the problem? | 13:16 |
| somlo | as in, I don't need them when synthesizing a self contained SoC with vexriscv embedded cpu? | 13:17 |
| somlo | I'm still confused about the architecture of litedram -- examples/litedram_gen.py appears to spit out a ready-for-synthesis build/gateware/ directory, with a .tcl file, etc. | 13:26 |
| somlo | it seems to include a CPU complete with bare-metal "firmware" that's supposed to speak "uart" | 13:27 |
| somlo | not clear how i'd get something I could connect to my own CPU/SoC, running my own bare-metal software | 13:28 |
| somlo | daveshah: when you built litedram for the ECP5 (https://twitter.com/fpga_dave/status/1097943452371820557) - what did your core_config struct look like? | 14:38 |
| daveshah | somlo: have a look at https://github.com/enjoy-digital/versa_ecp5 | 14:39 |
| tpb | Title: GitHub - enjoy-digital/versa_ecp5: Versa ECP5 SoC based on LiteX (at github.com) | 14:39 |
| somlo | does this: https://github.com/enjoy-digital/versa_ecp5/blob/master/versa_ecp5.py#L83 mean you ended up using Diamond to build it? | 14:51 |
| tpb | Title: versa_ecp5/versa_ecp5.py at master · enjoy-digital/versa_ecp5 · GitHub (at github.com) | 14:51 |
| daveshah | This branch uses nextpnr:https://github.com/daveshah1/versa_ecp5_dram/tree/trellis2 | 14:52 |
| tpb | Title: GitHub - daveshah1/versa_ecp5_dram at trellis2 (at github.com) | 14:52 |
| daveshah | but stuff isn't upstream yet so I wouldn't recommend it | 14:52 |
| somlo | I don't have Diamond, so if I do end up trying something on ecp5 it'll have to be the trellis version :) | 14:53 |
| daveshah | You'll need https://github.com/YosysHQ/nextpnr/tree/placer_heap_ddrn and https://github.com/SymbiFlow/prjtrellis/tree/ddrn and https://github.com/daveshah1/yosys/tree/ecp5improve | 14:54 |
| tpb | Title: GitHub - YosysHQ/nextpnr at placer_heap_ddrn (at github.com) | 14:54 |
| somlo | Thanks! I'll tinker with this for the next couple of days (mixed in with some dayjob related travel), and maybe it will all start making sense by the time I get back, so the questions will hopefully get correspondingly less silly :) Thanks (again) for all the help, btw! | 15:04 |
| _florent_ | somlo: in the standalone example, a cpu is embedded to do the initialization | 18:26 |
| _florent_ | somlo: the uart pins are exposed, but that's mostly for debug to ease debug is the calibration fails | 18:26 |
| _florent_ | somlo: you can leave it unconnected if you want, there are status pin that tells you when the calibration is done and the status | 18:27 |
| _florent_ | the default example is configure for 2 ports, you can reduce it to one if you only want one | 18:28 |
| _florent_ | configure/configured | 18:29 |
| _florent_ | but, you still need to connect the axi pins in your top since these pins are not I/Os | 18:29 |
| _florent_ | if you want to test a self contained SoC for the Nexys4DDR, there is a target: https://github.com/enjoy-digital/litex/blob/master/litex/boards/targets/nexys4ddr.py | 18:31 |
| tpb | Title: litex/nexys4ddr.py at master · enjoy-digital/litex · GitHub (at github.com) | 18:31 |
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