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| acathla | When uploading a litex+cpu design to a fomu, the code goes to flash and seems to be executed from there. Is there simple way to copy it to RAM? | 10:01 |
|---|---|---|
| acathla | xobs should know... | 10:04 |
| xobs | litex+cpu? No, that would require a second device to configure the FPGA. | 10:06 |
| xobs | Fomu EVT has a way to do that, but that is significantly larger. | 10:06 |
| tnt | I'm assuming he meant the riscv fw code, not the fpga bitstream. | 10:10 |
| scientes | when i was building from litex recently I fail with like 8500 LUTS in use | 10:32 |
| scientes | or like 70% too much | 10:33 |
| scientes | so something is seriously wrong | 10:33 |
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| acathla | scientes, you need to specify a --cpu-variant=simple or something like that | 11:35 |
| acathla | xobs, foboot is executed in SRAM, when I upload code for the VexRiscV it goes to SPI flash and is executed from flash too? Can't it be copied to SPRAM first? | 11:37 |
| acathla | With the llitex bios there is a mem test. I got 97KB/s but I had less, like <40KB/s when SPI flash was in 1x. So executing from flash is really slow. | 11:40 |
| acathla | I'm writing a foboot-like bootloader that will use infrared instead of USB, and will probably not have to flash new FPGA designs but only code for the RISCV. | 11:41 |
| acathla | And it's for a robot that has almost the same hardware than the fomu of course. | 11:42 |
| xobs | acathla: foboot is actually executed from ROM. It's special like that. | 12:40 |
| xobs | If you want code to execute from RAM instead of SPI, you can annotate the function with `__attribute__((.section(".data")))` to place it in the data section, which gets copied to RAM when your program starts. | 12:42 |
| xobs | Usually I create a new linker section called `.ramtext` and place stuff in it that way. For example: https://github.com/adafruit/circuitpython/blob/main/ports/litex/mphalport.c#L57-L58 | 12:43 |
| xobs | Another approach you can take is to manually place functions there by adding them to the linker script: https://github.com/adafruit/circuitpython/blob/main/ports/litex/boards/fomu/fomu-spi.ld#L47-L63 | 12:43 |
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| acathla | Ok, ROM made from Blocks or RAM in the FPGA. | 13:13 |
| acathla | xobs, that's perfect! | 13:13 |
| xobs | If you're making your own SoC core, you could do something like make your ROM execute an infinite loop, then manually load the program into RAM using the debugger. Add the DummyUSB device, add a UART with crossover, and be sure to set the `REBOOT_ADDR` register: https://rm.fomu.im/reboot.html#reboot-addr3 | 13:15 |
| tpb | Title: REBOOT Fomu Bootloader documentation (at rm.fomu.im) | 13:15 |
| xobs | Basically, have it so when the device first boots up, it enumerates as a USB device. Then use `wishbone-tool` to act as both a GDB server and a terminal (wishbone-tool -s gdb -s terminal --csr-csv build/csr.csv). If you place your test program entirely within RAM, you can load it with GDB, set `REBOOT_ADDR` to 0x10000000 (i.e. the start of RAM), then use `mon reset` to reset the CPU and run your program. | 13:20 |
| acathla | Ok, but that's just for testing | 13:21 |
| acathla | but nice to know it's possible | 13:21 |
| st-gourichon-fid | Thanks xobs for the hints! One minor adjustment: it's __attribute__((section(".data"))) without dot before section. | 13:26 |
| xobs | Ah, my mistake. I always get that wrong. | 13:26 |
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| st-gourichon-fid | Not a problem, lots of thanks. We are testing that. | 13:27 |
| st-gourichon-fid | xobs, we are exploring what you explained. | 13:30 |
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| acathla | memspeed() (in the default litex bios) on VexRiscV goes from 97KB/s executed from SPI to 1674KB/s executed from RAM (SPRAM). | 14:31 |
| st-gourichon-fid | Regarding memspeed(), strangely enough, we had an assembler error. We had to make our own copy of memspeed() and shorten it until assembler accepted. I can imagine some reasons, but unsure. | 14:41 |
| st-gourichon-fid | Error is : .s: Error: value of 380 too large for field of 1 byte at 258 | 14:42 |
| st-gourichon-fid | When I remove code in function, value decreases, and when below 256 code compiles. | 14:44 |
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| st-gourichon-fid | xobs, we are trying to see if there's a way to put "most" code in RAM. I tried with method "I don't think it will work but cheap to try", replacing all "} > rom" to "} > sram AT > rom" and of course it crashed horribly. | 15:12 |
| xobs | You just need to place the start section in flash, then move .text into the .data section. | 15:13 |
| st-gourichon-fid | Earliest code (crt0, things before main) has to be in ROM, then all C-level code "could" be in RAM. | 15:13 |
| st-gourichon-fid | Just moving the line "*(.text .stub .text.* .gnu.linkonce.t.*)" from the text section declaration to the data section declaration appears to do the trick. | 15:26 |
| st-gourichon-fid | because the existing text section declaration says "*crt0*(.text)" which already guarantees that crt0 is in .text section. | 15:27 |
| xobs | Ooh, neat. Yay! | 15:27 |
| st-gourichon-fid | Thanks for your hints! | 15:27 |
| st-gourichon-fid | Our current linked.ld os basically this one: https://github.com/litex-hub/fpga_101/blob/master/lab004/firmware/linker.ld | 15:28 |
| st-gourichon-fid | ah not this one. | 15:28 |
| st-gourichon-fid | That one: https://github.com/enjoy-digital/litex/blob/e32e8c069bda2255b8b6b10520e6698a20bd10a0/litex/soc/software/bios/linker.ld#L39 | 15:29 |
| st-gourichon-fid | confirmed. | 15:30 |
| scientes | what do i type to boot, again? | 15:48 |
| scientes | after I load a rom, I have to type something after plugging it in, in order to run it | 15:50 |
| xobs | `dfu-util -e`? | 15:58 |
| scientes | yeah that's it | 16:11 |
| scientes | to add confusion, the firmware my fomu shipped didn't work that way | 16:12 |
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