Monday, 2020-07-20

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acathlaI have a design with infrared uarts which PHY is at 48MHz. It doesn't pass the timings with usb_debug. How can I make the two 48MHz clocks independant. Without usb_debug, the design takes 12% of ICESTORM_LC, with debug 35%10:54
acathlaOr is there magic somewhere...10:55
xobsLet me see where the 48 MHz clock comes from...11:22
xobsAh right, I ended up with the 48 MHz clock derived directly from the crystal, with a separate 12 MHz clock coming from the PLL: https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/fomu.py#L86-L11311:24
tpbTitle: litex-boards/fomu.py at master · litex-hub/litex-boards · GitHub (at github.com)11:24
xobs(Earlier approaches generated a 48 MHz clock by multiplying a flopped 12 MHz clock up by 4x, due to a poorly-documented PLL)11:25
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acathlaxobs, do you know why the USB part have an influence on my UART part? It's only linked by the wishbone bus which is only at 12MHz.12:37
xobsThe ICE40UP5K can't run a lot of high-speed logic. The 48 MHz domain is needed to run the USB 4x oversampling core. Your part is also in the 48 MHz domain, which means they share timing dependencies.12:40
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