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| promach3 | How does transfer bitstream to FOMU since there is no JTAG ? What if the usb part of the FOMU is bricked ? | 02:23 |
|---|---|---|
| promach3 | * How to transfer bitstream to FOMU since there is no JTAG ? What if the usb part of the FOMU is bricked ? | 02:23 |
| xobs | That's why Fomu doesn't auto-boot, and why the bootloader doesn't allow you to overwrite the first 256 kB of flash. | 02:24 |
| promach3 | xobs: 256kB of flash -> is this external SPI flash ? | 02:24 |
| xobs | Yes, the bitstreams are stored on external SPI flash. | 02:25 |
| xobs | When you upload a new bitstream, it goes into "slot 3". The bootloader always loads from "slot 0". | 02:25 |
| xobs | When you say "execute program", or upload a new bitstream, it jumps to "slot 3". But cycling power always causes it to start again from "slot 0". | 02:26 |
| promach3 | ok | 02:26 |
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| MadHacker | xobs: Think touch can be made reliable enough to have "hold button for 5s to prevent autoboot" and update the bootloader to handle that? | 09:11 |
| MadHacker | Sorry, passing thought. | 09:11 |
| xobs | MadHacker: that was a thought, thought right now the captouch stuff hasn't been widely tested, and it's rather large in terms of LC count. | 09:12 |
| MadHacker | As in, doesn't fit? | 09:16 |
| xobs | Not currently, no. | 09:16 |
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| acathla | Can I use litex_server with Fomu (on USB)? xobs, _florent_ ? | 10:13 |
| xobs | acathla: I believe so. There are command line arguments to set it up. | 10:14 |
| acathla | Like: litex_server --usb --usb-vid 1209 --usb-pid "5bf0" ? | 10:14 |
| xobs | However, you can also use `wishbone-tool` in place of `litex_server` to server wishbone to remote devices e.g. to connect `lxterm`: `wishbone-tool -s wishbone` | 10:14 |
| acathla | it answers : ValueError: invalid literal for int() with base 0: '5bf0' | 10:14 |
| xobs | Maybe you need to specify `0x5bf0`? | 10:15 |
| acathla | haha right! it works =) | 10:15 |
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| acathla | If I just switch the two usb lines in platform/fomu-evt.py and I try to build workshop.py --board evt, I got an error: | 13:54 |
| acathla | ERROR: PLL 'SB_PLL40_CORE' couldn't be placed anywhere, no suitable BEL found. | 13:54 |
| acathla | is there a hardcoded pin somewhere? | 13:56 |
| xobs | That sounds like it's trying to place two PLLs for some reason. Do you have the error somewhere? | 13:57 |
| acathla | You mean the whole logs online? | 13:58 |
| xobs | Yeah. Well, mostly interested in the last ~50 lines. | 13:59 |
| acathla | not yet | 13:59 |
| acathla | https://pastebin.com/ZKpLMpgY | 14:02 |
| tpb | Title: PLL_placement_error - Pastebin.com (at pastebin.com) | 14:02 |
| xobs | Your system clock is 12 MHz? | 14:03 |
| acathla | I guess, I didn't change things except inverting some pins in platform | 14:04 |
| acathla | I see only one PLL in the top.v | 14:05 |
| xobs | It's as if your pnr tool doesn't know about plls. Here's what last night's build for foboot resulted in: https://ci.betrusted.io/job/foboot/114/console | 14:08 |
| tpb | Title: foboot #114 Console [Jenkins] (at ci.betrusted.io) | 14:08 |
| xobs | Oh. | 14:08 |
| xobs | I see. | 14:08 |
| xobs | Yours has `Info: constrained 'usb_pulldown' to bel 'X12/Y31/io1'` whereas foboot has `constrained PLL 'SB_PLL40_CORE' to X12/Y31/pll_3`. Perhaps you assigned the pad to a GPIO, but forgot to update the pin mapping? | 14:09 |
| xobs | Since the same X/Y is already in use. | 14:09 |
| acathla | But I only use litex, which generates a .pcf with pin numbers | 14:12 |
| acathla | I'll rgrep that... | 14:13 |
| xobs | Right, but if you assign pin 44 to both the crystal and a usb pullup pin, litex will happily pass that through but nextpnr will choke on it. | 14:13 |
| xobs | Check the generated pcf file and see if one pad isn't assigned to two signals. | 14:14 |
| acathla | Nope, all different. | 14:15 |
| xobs | Which pad is the crystal connected to? | 14:15 |
| xobs | clk48 | 14:15 |
| acathla | pin 44 | 14:15 |
| xobs | and usb_pulldown? | 14:16 |
| acathla | Info: constrained 'clk48' to bel 'X6/Y0/io1' in the logs | 14:16 |
| xobs | Good point, foboot is generated for wlcsp parts. | 14:16 |
| acathla | pulldown pin 35 instead of pin 36, and pullup pin 36 instead of 35 (on EVT) | 14:17 |
| acathla | but for SG48, evt, it works fine unless I switch those pins | 14:17 |
| acathla | and it worked when building foboot with pins swaped, it's the workshop.py that doesn't work today. | 14:18 |
| acathla | I did a lot of git pull, I should try again foboot... | 14:18 |
| xobs | When building for EVT it also says `constrained PLL 'SB_PLL40_CORE' to X12/Y31/pll_3`. | 14:21 |
| xobs | It's odd you'd see that, especially since it's not like we use the differential pairs' ability -- they should be entirely interchangeable. | 14:22 |
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| acathla | and foboot seems to build correctly, routing still running. | 14:27 |
| acathla | pulldown is useless, right? If I remove it, it works! | 14:43 |
| xobs | Yeah, pulldown is useful if you want low speed support. It was an option on the EVT board, because when you build an EVT version you stick all the options on. | 14:44 |
| rr1 | hello, a new fomu user here. | 14:46 |
| rr1 | I did all of the workshop tutorials and they are working fine | 14:46 |
| mithro | https://github.com/BrunoLevy/learn-fpga -- RV32 on an icestick! | 14:46 |
| tpb | Title: GitHub - BrunoLevy/learn-fpga: Learning FPGA, yosys, nextpnr, and RISC-V (at github.com) | 14:46 |
| rr1 | now I having trouble creating a vexriscv+blinky rom soc with litex | 14:47 |
| rr1 | I build and flash but no usb and no led blinking | 14:47 |
| rr1 | To debug, I removed the core and added the usb bridge and checked that the firmware is correctly in rom and that I can toggle the led with wishbone bridge | 14:47 |
| rr1 | So I know that the bus, led, rom, usb hardware are ok | 14:48 |
| rr1 | Any idea how I can continue debugging from here? | 14:48 |
| xobs | rr1: if your vexriscv doesn't have any USB drivers (i.e. tinyusb), then you may want to start with the dummyusb implementation and enable debug mode so you can poke things even with the cpu running. | 14:49 |
| rr1 | I thought that was not possible because I am getting this error: | 14:51 |
| rr1 | ERROR:SoC:EventManager not found in usb SubModule. | 14:51 |
| xobs | That's because it's still trying to add an interrupt for the usb block, even though the dummyusb module doesn't have one. | 14:52 |
| rr1 | oh, thanks, build issue solved | 14:53 |
| rr1 | the error message is cryptic though | 14:53 |
| xobs | I agree. | 14:54 |
| xobs | I think what it's trying to say is "The event manager found an object called `usb`, which means there should be a property on it called `.ev`, but that wasn't there, so I don't know what to do" | 14:55 |
| rr1 | xobs: so i think, my next step is to work with the debug variant + dummyusb, have a jtag and check the state of the core, does this sound reasonable? | 15:05 |
| xobs | That does, yeah. Poke at it with wishbone-tool, either with a CPU debugger or just peek and poke, and get a feel of what could be going wrong. | 15:05 |
| rr1 | I found the issue; endieness. In lxsocsupport/firmware.py:24 in FirmwareROM class, I changed the unpack endiness, the firmware is running, thanks xobs! | 15:33 |
| rr1 | maybe that function needs a parameter to set the endieness | 15:35 |
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| xobs | Cool! | 16:31 |
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