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| JoelS | I finished going through the workshop. On Windows, at least, the litex documentation and/or build seems to be incomplete -- it produces a .bin file, but not a .dfu file. | 00:25 |
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| xobs | JoelS: that's a good point. When the workshop was first developed, we didn't ship dfu-util with the toolchain (well, we didn't _have_ a toolchain), so we couldn't guarantee `dfu-suffix` existed. But now we can! | 01:03 |
| xobs | The `.bin` file should work, but we ought to be building a `.dfu` file as well. | 01:03 |
| xobs | JoelS: hmm... it looks like it ought to add the `.dfu` file: https://github.com/im-tomu/fomu-workshop/blob/master/litex/workshop_rgb.py#L185 | 01:06 |
| tpb | Title: fomu-workshop/workshop_rgb.py at master · im-tomu/fomu-workshop · GitHub (at github.com) | 01:06 |
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| acathla | Previously, on #tomu : <acathla> Anybody tried to make an ADC on an iCE40 using the diffential inputs? | 08:59 |
| acathla | <tnt> acathla: yeah. | 08:59 |
| acathla | <tnt> (I'm actually writing some code related to that right now :p) | 08:59 |
| acathla | tnt, any success? | 08:59 |
| tnt | acathla: yeah, works fine. | 09:08 |
| acathla | Cool! | 09:09 |
| acathla | tnt, how did you do it? | 09:09 |
| acathla | I saw different techniques | 09:10 |
| tnt | In this case I'm timing the charge of a capacitor and compare the rising voltage against the one I'm trying to measure. | 09:11 |
| tnt | I want to give delta sigma a shot, but didn't get around to it yet. | 09:11 |
| acathla | tnt, is your code online somewhere? | 09:12 |
| tnt | https://pastebin.com/ckDBDnH1 | 09:17 |
| tpb | Title: [VeriLog] /* * sense.v * * vim: ts=4 sw=4 * * Copyright (C) 2019 Sylvain Munaut (at pastebin.com) | 09:17 |
| tnt | It's really just a counter ... (well, two, because I time both charge and discharge to get two measurements). | 09:18 |
| tnt | The result is a time value that needs to be converted to voltage using RC formulas and also calibration factors to remove all the imprecisions. | 09:19 |
| acathla | tnt, thank you. | 09:21 |
| acathla | I just found that : http://www.latticesemi.com/en/Products/DesignSoftwareAndIP/IntellectualProperty/ReferenceDesigns/ReferenceDesign03/SimpleSigmaDeltaADC | 09:22 |
| tpb | Title: Simple Sigma-Delta ADC - Lattice Semiconductor (at www.latticesemi.com) | 09:22 |
| MadHacker | Didn't bunnie publish some stuff on this? | 09:22 |
| MadHacker | https://www.bunniestudios.com/blog/?page_id=24 | 09:22 |
| MadHacker | I guess classic PC joyport stuff, too. :) | 09:24 |
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| xobs | So a simple "dummyusb" implementation (no bridge) with a blink takes up 674 LCs. It enumerates, but there's not much you can _do_ with it. | 11:41 |
| xobs | It's a starting point, though! | 11:41 |
| MadHacker | xobs: I ended up going back to dummyusb, but I'm splitting it up into a front-end and a back-end, so there's a ControlEndpoint (and FifoEndpoints) that connect to the main bit of it. | 11:42 |
| MadHacker | The only actual stuff that needs added is a bunch of muxes really. | 11:42 |
| MadHacker | Code separation's the bigger hassle. | 11:43 |
| MadHacker | *Almost* back to where I started. I'll try and find time this evening to finish it off. | 11:43 |
| MadHacker | Thanks, though, dummyusb's been a lot easier to understand than the other implementations. | 11:43 |
| MadHacker | (also it only has deps on migen, not litex, which is a big help for me!) | 11:44 |
| xobs | MadHacker: I wonder if you could get away with doing something like `self.comb += [If(usb_core.endp == 1, fifo.din.eq(usb_core.data_recv_payload), fifo.we.eq(usb_core.data_recv_payload))]` | 11:45 |
| xobs | Then wire up `fifo.dout` and `fifo.readable` to your 6502 somewhere. | 11:46 |
| MadHacker | Dangerously close; you'd need to sort out the acknowledgements, and I haven't figured out if dtb is per-endpoint. | 11:47 |
| MadHacker | But yeah. | 11:47 |
| xobs | dtb is per-endpoint, yeah. | 11:47 |
| xobs | It gets reset on SETUP, but you don't need to worry about that in this design. | 11:47 |
| MadHacker | Just pushed to show (not ready to use yet) - https://github.com/jamesacraig/6502-on-fomu/blob/master/fomu_usb_cdc.py - L#14, I have a thing that builds muxes from a list, and L#361 I'm just wiring up each endpoint's version of the signals as appropriate. | 11:50 |
| tpb | Title: 6502-on-fomu/fomu_usb_cdc.py at master · jamesacraig/6502-on-fomu · GitHub (at github.com) | 11:50 |
| MadHacker | So the ControlEndpoint class is meant to be basically the guts of dummyusb minus the shared stuff that's across the whole device. | 11:50 |
| MadHacker | That's where I'm going with it just now, anyway. I could hack it like you've suggested, but it seems nicer to try and build something a little more general, even if it's just for code readability. | 11:51 |
| MadHacker | Hm, spotted a bug in the mux thing, doesn't remove default from the list it iterates over. Oh well. | 11:53 |
| xobs | I'm also not sure if this actually works in migen's syntax: https://github.com/jamesacraig/6502-on-fomu/blob/master/fomu_usb_cdc.py#L391 | 11:54 |
| tpb | Title: 6502-on-fomu/fomu_usb_cdc.py at master · jamesacraig/6502-on-fomu · GitHub (at github.com) | 11:54 |
| xobs | But if it generates the correct Verilog, then hooray! | 11:55 |
| MadHacker | Well, it's python syntax. It generates a list that looks like [endpoints[0].data_recv_put.eq(usb_core.data_recv_payload & 0==endpoint)] | 11:55 |
| MadHacker | I might have a missing () around the == clause, but that's about all. | 11:56 |
| xobs | I was thinking more about this: https://github.com/m-labs/migen/issues/137#issuecomment-484351624 | 11:56 |
| MadHacker | Ah, I found that the other day. | 11:56 |
| MadHacker | I haven't checked the verilog output yet (still work to do before I can!) but if it breaks, then a quick migen.wrap() around the 0==endpoint will fix it. | 11:57 |
| xobs | You're using `&` though, so maybe it's fine! | 11:57 |
| MadHacker | That issue was near-ragequit-inducing. | 11:57 |
| MadHacker | wrap() calmed me down again. :) | 11:58 |
| acathla | MadHacker, nice hack (hackDAC)! | 12:01 |
| MadHacker | acathla: Not mine, bunnie's! | 12:01 |
| acathla | Oh, the same bunnie from the bunnie & tim conference at CCC? | 12:02 |
| MadHacker | Presumably. There's only one notable bunnie, as far as I'm aware. :) | 12:05 |
| MadHacker | xobs: https://paste.debian.net/1098389/ - looks OK, I probably need the () around the == clause, but nothing more elaborate. | 12:08 |
| tpb | Title: debian Pastezone (at paste.debian.net) | 12:08 |
| MadHacker | & vs and is important right enough tho. | 12:08 |
| MadHacker | Definitely wrong with and. | 12:08 |
| xobs | Hooray! That's good to know. | 12:08 |
| MadHacker | Thanks for spotting it, though, since the precedence was wrong anyway. :) | 12:11 |
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| mithro | xobs: https://github.com/xobs/valentyusb/pull/4 | 18:28 |
| tpb | Title: WIP: Adding sphinx docs by mithro · Pull Request #4 · xobs/valentyusb · GitHub (at github.com) | 18:28 |
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| mithro | xobs: https://github.com/enjoy-digital/litex/pull/254 | 22:08 |
| mithro | https://github.com/enjoy-digital/litex/pull/253 | 22:09 |
| tpb | Title: WIP: Enable link-time-optimization on LiteX builds by mithro · Pull Request #253 · enjoy-digital/litex · GitHub (at github.com) | 22:09 |
| mithro | xobs: https://github.com/renode/renode/releases/tag/v1.8 | 22:23 |
| tpb | Title: Release Renode 1.8 · renode/renode · GitHub (at github.com) | 22:23 |
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