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| MadHacker | https://hackaday.com/2019/03/20/introducing-the-shitty-add-on-v1-69bis-standard/ I had not seen this before, but I'm kind of there for it. Tomu/fomu to v1.69bis Shitty Add-On standard adapter? :) | 09:32 |
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| MadHacker | Little sad that standard is not pmod-compatible too, though. | 09:34 |
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| xobs | It's almost pmod. Almost. | 10:19 |
| xobs | Also, I'm redesigning the USB interface so it can have an arbitrary number of endpoints. | 10:20 |
| xobs | I was having a lot of trouble with the migen simulator (1) being slow, and (2) not dealing with clock domains well at all. | 10:20 |
| xobs | So I'm in the process of learning cocotb, which has the nice property that much of the Python code just works: https://github.com/xobs/valentyusb/blob/tri-fifo/sim/test-eptri.py | 10:21 |
| tpb | Title: valentyusb/test-eptri.py at tri-fifo · xobs/valentyusb · GitHub (at github.com) | 10:21 |
| MadHacker | For my little play-about 6502 thing, I was just doing test in verilog-space after calling the migen converter. | 10:28 |
| MadHacker | Not used the migen test infrastructure, although I gather it's perfectly functional. | 10:29 |
| xobs | MadHacker: that's what I'm doing, too. I transform the migen code to Verilog, then I access that from Cocotb. | 10:29 |
| MadHacker | A 10-second google says cocotb looks nice though. | 10:29 |
| MadHacker | Ahha. | 10:29 |
| xobs | I expose the wishbone signals and the USB signals (and some clock signals as well) out the top module, and interact with it that way. | 10:30 |
| MadHacker | OK. Can it poke at internals? | 10:30 |
| MadHacker | Or do you have to explicitly expose everything? | 10:30 |
| xobs | I suppose it could, but migen mangles names when it builds. | 10:30 |
| xobs | The closest I can do is get memory addresses for things on the Wishbone bus, and control things that way. | 10:31 |
| MadHacker | One of my friends has a CPUless GDB stub in verilog for this sort of thing actually. | 10:32 |
| xobs | That's a neat hack. I'm sure it runs nicely under Verilator. | 10:32 |
| MadHacker | Connect it up to the bus as a bus master or to the CPU's register bank and you can poke whatever you like via gdb. | 10:32 |
| MadHacker | It does. Works for his Amiga accelerators mostly. | 10:33 |
| tnt | xobs: micropython on the fomu, were you running it from flash or loaded in sram ? | 11:32 |
| xobs | tnt: flash - it comes to around 130k, so it won't fit into ram. | 11:36 |
| tnt | xobs: ok. I was looking at porting micropython to the icebreaker too with tinyusb and my core, but ATM it's 80k without the usb stack (using compressed instruction set) and there is no modules basically ... | 11:42 |
| xobs | I think I got it down to about that much, but you're right there's not much you can do with that. | 11:43 |
| tnt | Did you create modules to allow to control the fomu hw ? | 11:52 |
| xobs | A few. Overall it was a proof of concept. | 12:08 |
| xobs | I'll build a better version once I have the USB stuff working to the point where I can have more than two endpoints. | 12:09 |
| xobs | tnt: https://github.com/xobs/micropython/tree/fomu?files=1 | 12:10 |
| tpb | Title: micropython/ at fomu · xobs/micropython · GitHub (at github.com) | 12:10 |
| tnt | xobs: what's the issue atm with more than 2 ep ? | 12:24 |
| xobs | tnt: the current USB system, `epfifo`, takes 200-400 LCs per endpoint. So something like circuitpython, which has 8 IN and 8 OUT endpoints, really is not doable. | 12:26 |
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| xobs | tnt: how does your method work? I seem to recall you said it allowed for arbitrary operations. | 13:12 |
| hegemoOn | matin | 13:17 |
| tnt | xobs: you mean my usb core ? Well, there is just no logic at all that's "per end point", all the states is stored in a RAM, nothing in register. | 13:18 |
| tnt | So when a setup token is received, it goes look up all the info it needs for that transaction (ep type, status, packet size, if there is data pending, ...) and when the transaction is done, it writes back all the result and state (liek DT, ...). | 13:20 |
| xobs | That sounds useful! And maybe that's what mithro was trying to do with "epmem". | 13:21 |
| tnt | xobs: alternatively you could also just wrap my core in migen :p jk. | 13:23 |
| xobs | Well, I'm now very certain the PHY stuff is good, and the MAC stuff can be played with. | 13:25 |
| xobs | And now that I have this cocotb testbench, I can get to work on finding a better USB<->CPU interface. | 13:25 |
| MadHacker | How many USB cores do we have? ;) | 13:30 |
| MadHacker | Now I want to see if I can pack one into this HX1K. :D | 13:31 |
| xobs | MadHacker: for valentyusb, there's one PHY layer, with two well-supported MAC layers and a third MAC layer that I'm working on. | 13:31 |
| xobs | You might be able to trim some stuff and get the "dummyusb" working on an HX1K. I think it's about 1400 LCs unoptimized. | 13:32 |
| xobs | ...but that'll get you a full Wishbone bus as well. Maybe tnt has one that is more suitable for it. | 13:32 |
| tnt | Well, I don't have an equivalent of dummyusb, my core needs a softcore to run the stack. Maybe the SERV riscv running off flash could fit. | 13:34 |
| tnt | (usb core itself is < 600 LCs) | 13:34 |
| xobs | Also, on the HX1K you might be able to just stick it all in the 48 MHz domain, which could save some LCs. | 13:35 |
| MadHacker | Mm. Context, apart from generic "playing with stuff" - I build blinky light controllers for the events industry. Mostly tiny microchip PIC based widgets. 8-bit cores are just fine for what I do, but they need reprogrammed in situ often, so USB would be handy. Rather than use a fatter processor for some of the bigger jobs, I could use an FPGA with some proper peripherals for the LED driver bits, and a very | 13:36 |
| MadHacker | small softcore. | 13:36 |
| MadHacker | The smaller the FPGA I can use the better. The HX1K is overkill on the small thing, of course. | 13:36 |
| xobs | Well, that's what the dummyusb core was designed to do -- provide a Wishbone master and nothing else. | 13:36 |
| xobs | See https://github.com/xobs/teardown2019-workshop/blob/master/litex/workshop_rgb.py for example | 13:37 |
| tpb | Title: teardown2019-workshop/workshop_rgb.py at master · xobs/teardown2019-workshop · GitHub (at github.com) | 13:37 |
| MadHacker | Sure, but wishbone itself is already much bigger than I need. 8-bit processors are fine for this. | 13:37 |
| xobs | (I really need to move that elsewhere...) | 13:37 |
| ssb | there is also https://github.com/avakar/usbcorev in Verilog (don't know how it is related to other works) | 13:37 |
| tpb | Title: GitHub - avakar/usbcorev: A full-speed device-side USB peripheral core written in Verilog. (at github.com) | 13:37 |
| MadHacker | I did a quick port, just to try it out, of Arlet's CPU's ALU to migen yesterday. That went easy, so I might do a migen'd up 6502 for fun, too. | 13:38 |
| MadHacker | Obviously an ALU is trivial, but it was OK for setting expectations of difficulty. | 13:38 |
| MadHacker | Thanks for the links, I'll take a nosey. | 13:39 |
| MadHacker | Also got that thing down to 783LCs with RAM and ROM BTW. My support logic was crap. | 13:44 |
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| tumbleweed | 59 | 21:54 |
| tumbleweed | grr | 21:54 |
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