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| xobs | ssb: mithro is correct. For the Hacker boards, I think there is GND and Power on those pads, but for Production we edge-plate them so they're easier to hit. So for Production you have no source for GND or +3.3V. | 01:20 |
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| ssb | mithro, xobs: thanks! That is great. | 05:31 |
| xobs | ssb: :D I'm really looking forward to seeing what people do with them. | 05:32 |
| ssb | for me that will depend on how much data rate the usb softcore will be able sustain ) | 05:35 |
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| xobs | That depends on how you use it. I'd like to do a version of the softcore that doesn't require a CPU, for example. It shouldn't be too difficult, since the rest of the pieces are all validated. | 05:37 |
| xobs | That would be nice and deterministic, and should sustain a high throughput. Relatively speaking, of course. | 05:39 |
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| pollo | xobs: hey, I've been unable to build micropython for the fomu: https://share.riseup.net/#vJLqV_cY7f9gmwDWSs2fMw | 06:06 |
| tpb | Title: share.riseup.net (at share.riseup.net) | 06:06 |
| pollo | Should I open a bug report? | 06:06 |
| pollo | I'm not sure if you folks intent to work on it or if it was just a proof of concept for now | 06:06 |
| xobs | pollo: right now it's a proof-of-concept. Is this on the Raspberry Pi image? | 06:07 |
| pollo | Yeah | 06:07 |
| xobs | Interesting. That makes it super reproducable then :) | 06:07 |
| xobs | I've finally settled on an approach that I think is easy-yet-robust, and we'll have to see just how doable it is. | 06:08 |
| pollo | I used the latest git commit though (not the latest release) if that matters | 06:08 |
| xobs | But the inital batch of Fomu units will ship with the DFU bootloader. | 06:08 |
| pollo | I've been able to make that work (foboot) though :9 | 06:09 |
| xobs | I'm going to work on a more advanced MSC-based bootloader, which we'll release when it's ready. The DFU bootloader will still be the "failsafe" one, but once the "main" bootloader is available it'll be more for recovery. | 06:09 |
| pollo | Ah, interesting | 06:09 |
| xobs | The "main" bootloader will read the SPI flash as a FAT12 filesystem, starting at offset 0x40000. It'll support the concept of "interpreters", one of which will be Micropython. | 06:10 |
| xobs | So micropython will be just a program on the FAT12 filesystem, and it'll interpret your .py file. | 06:10 |
| xobs | As a result, micropython support will have to come after the main bootloader support. | 06:11 |
| pollo | sure, I was mainly trying to test all the things to help out | 06:33 |
| xobs | I appreciate it! I'll look at it now. | 06:34 |
| xobs | My guess is that the toolchain I built doesn't have rv32i support. | 06:34 |
| xobs | I think that's it, yeah. Initially I wanted to add a multiply unit, but it ended up being too big, so we're shipping without one. | 06:40 |
| xobs | Once we have the usb core optimized, and once nextpnr gets better at inferring 17-bit multplies, we'll be able to move back to rv32im. | 06:41 |
| xobs | But for now, I will rebuild the toolchain for rv32i (i.e. no multiply unit), which should fix that problem. | 06:42 |
| tnt | xobs: huh ? I thought all toolchain supported going to rv32i with proper flags ( -march=rv32i -mabi=ilp32 ) | 06:53 |
| xobs | tnt: that was my guess, but the issue reported by pollo appears to be that the standard libraries we ship are for rv32im only. | 06:54 |
| tnt | oh, ok. Yeah looking at both toolchain I have they ship with a bunch of variants of the standard libs. | 06:56 |
| xobs | Yeah, I built the riscv toolchain as non-multilib, because multilib is complicated and takes more time. | 07:02 |
| tnt | btw, I've been comparing the vex and picorv32. I was excpecting the vex to be much faster but in the end, not so much :/ It takes a bit less cycles per instruction on average, but it also has a lower fmax. | 07:09 |
| xobs | tnt: interesting. is this on ice40? | 07:14 |
| tnt | yes on the up5k. | 07:15 |
| tnt | That was the 'min' variant. The variant with icache is a bit faster but consumes also quite a bit more resources. | 07:16 |
| xobs | there are a few knobs we can tune. From what I gather the ones in the "Vexriscv-Verilog" directory are all rather old. But maybe not. I've been trying to get it as small as possible while still being reasonably compliant. | 07:17 |
| tnt | They've been updated recently because I found an issue when testing :) (it only affected simulation though) | 07:18 |
| xobs | Compiling toolchains is so very difficult. | 08:03 |
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| tnt | A bit more testing: Switching from wishbone to a pipelined bus for instruction fetch and enabling static branch prediction seems to have very positive effects. ~ 150 more LCs but I can probably live with that. Need to do a more complete system and try it on actual hw. | 13:51 |
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