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xobs | Yay, I managed to get the sigrok-cli decoder working with gtkwave! Thanks, tnt. Any idea why it fails sometimes? If I just keep pressing "Ctrl-R", then about 15% of the time it decodes wrongly. | 07:26 |
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* xobs uploaded an image: image.png (23KB) < https://matrix.org/_matrix/media/v1/download/matrix.org/hRtbHyyelJEfVVOdnlDyYCEw > | 07:27 | |
tnt | xobs: I'm not sure tbh, but I didn't really did deep either. I guess I should write a debug mode where it saves the input vcd to a different file and see if there are variations. | 07:30 |
xobs | Ah, so you noticed that as well? Seems that it doesn't necessarily like the skew. But oh well. | 07:31 |
tnt | and for some reason if I use lxt2 source file instead of vcd ... can't get it to work at all. | 07:31 |
xobs | Phew, the testbench works much better if I actually drive clk48. Makes sense that the PLL isn't simulated. They're complicated. | 07:51 |
tnt | Ahah, yeah having a clock helps. | 07:56 |
rohitksingh | xobs: fomu-flash doesn't result in any activity on the SPI bus...just initially it asserts (pulls down) CRESET pin....On the other hand if I use python spidev library, I can see some activity on the SPI bus.... these are my connections https://www.dropbox.com/s/k2re3cp8mz499lw/fomu-flash-diff.png?dl=0 | 08:07 |
tpb | Title: Dropbox - fomu-flash-diff.png (at www.dropbox.com) | 08:07 |
rohitksingh | I followed the pinouts provided in the readme here: https://github.com/im-tomu/fomu-flash | 08:08 |
tpb | Title: GitHub - im-tomu/fomu-flash: Utilities to flash Fomu from a Raspberry Pi (at github.com) | 08:08 |
rohitksingh | anytime I might be missing here? | 08:08 |
rohitksingh | *anything | 08:08 |
xobs | rohitksingh: Those definitions don't look quite right. Did you specify the header pins instead of the BCM pins? For example, your S_MOSI is BCM19, which is pin 35 on the header (and is a hardware MISO pin), and your S_CLK is BCM23, which is on pin 16 o fthe header. | 08:11 |
xobs | The default S_MOSI is BCM10, which is located on pin 19 of the header. | 08:11 |
rohitksingh | xobs: facepalm! indeed I used "header" pin numbers | 08:12 |
xobs | Likewise, the default S_MISO is BCM9, which is located on pin 21 of the header (going based on https://pinout.xyz/) | 08:12 |
tpb | Title: Raspberry Pi GPIO Pinout (at pinout.xyz) | 08:12 |
rohitksingh | xobs: thank you so much! let me try with correct values :) | 08:12 |
xobs | rohitksingh: no problem! You can also remap them without compiling by specifying a command line switch. I forget which one it is. | 08:13 |
xobs | Also, note that the F_RESET is different on the very first Raspberry Pi devices, which is why it's not a #define. | 08:13 |
rohitksingh | yup it was "-g i:PIN" like that | 08:14 |
rohitksingh | sure, thanks! let me try | 08:14 |
rohitksingh | :) | 08:14 |
rohitksingh | xobs: so the default pin mapping in your code itself was the correct one, lol...it's working now! \o/ https://www.dropbox.com/s/edkjxgv9lokhjme/fomu-flash-spi-id.png?dl=0 | 08:24 |
tpb | Title: Dropbox - fomu-flash-spi-id.png (at www.dropbox.com) | 08:24 |
rohitksingh | time to set up ice40 toolchain and try some basic designs | 08:25 |
xobs | Hooray! \o/ | 08:25 |
xobs | Are you using your own Raspberry Pi image/ | 08:25 |
rohitksingh | yup the standard raspbian | 08:25 |
rohitksingh | do we have separate image for fomu development? | 08:26 |
xobs | I ask because there are images at https://github.com/im-tomu/fomu-pi-gen/releases -- I really ought to upload a replacement that has lm32 support as well. | 08:26 |
tpb | Title: Releases · im-tomu/fomu-pi-gen · GitHub (at github.com) | 08:26 |
rohitksingh | oooh, that is awesome! it will spare me the headache of setting up toolchain! thanks again! let me try the image :) | 08:27 |
xobs | You can just install packages, though. | 08:27 |
rohitksingh | oh okay | 08:27 |
xobs | https://github.com/im-tomu/fomu-pi-gen/tree/master/stage2-fomu/04-fomu/files | 08:27 |
tpb | Title: fomu-pi-gen/stage2-fomu/04-fomu/files at master · im-tomu/fomu-pi-gen · GitHub (at github.com) | 08:27 |
xobs | Actually, that would also be a nice thing to have. Just packages, for people who already have an install. | 08:27 |
rohitksingh | nice, all the packaged toolchains are available! I spot lm32 too there, added probably 4 days back. So maybe that's why you mentioned the last release image doesn't have lm32? | 08:32 |
xobs | It doesn't, and I haven't tested it yet. I actually haven't tested the "Pre-release" image either, though I assume it works. But that's the major reason why I haven't promoted it to "Latest release". | 08:33 |
rohitksingh | ah okay | 08:33 |
rohitksingh | still I have to say these packaged version have made the setting up part as easy as I can expect! props to you xobs! | 08:34 |
xobs | Yay! | 08:34 |
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xobs | It's not particularly fast, but it's quick to set up. | 08:45 |
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tnt | xobs: btw, did you have a look at the patch I posted see if it did anything wrt to the corruption on real hw ? | 09:35 |
xobs | tnt: Let me set up some real hardware and give that a shot. | 10:05 |
tnt | xobs: note that (1) here at least I noticed that the clock constraint are not applied correctly because the post-synthesis net name for the clk doesn't match what's in the pre_pack.py file generated by migen. (2) it didn't meet timing without adding the "-relut -dffe_min_ce_use 4" options to yosys synth_ice40 for me. | 10:12 |
xobs | That's a little concerning. The clock stuff, at least. What do those arguments to synth_ice40 do, and what are the tradeoffs of using them? | 10:18 |
tnt | 'relut' applies another optimization pass to pack more into LUTs. Tradeoff is ... well it's one more pass, takes a tiny bit of time I guess. | 10:22 |
tnt | 'dffe_min_ce_use 4' prevents yosys from generating a Clock Enable signal that's used by less than 4 FFs. Yosys tends to be pretty agressive into generating CE (vs a MUX with the old value) and on the ice40 CE is shared between 8LCs, so if you have a CE used by only one FF, you wasted 7 LCs. | 10:24 |
tnt | So far I have never seen a case where those two options had a global negative effect on either size or timing. | 10:24 |
xobs | I'll add those to the Foboot synthesis, then. And see if I can't fix the clk48 generation. | 10:29 |
xobs | Need to head out soon, though :( | 10:30 |
xobs | I wonder if that's a bug in nextpnr, then... | 10:35 |
xobs | The top.v has `always @(posedge usb_48_clk) begin` for example, but nextpnr reports `Warning: net 'usb_48_clk' does not exist in design, ignoring clock constraint` | 10:35 |
xobs | Or maybe Yosys is doing something to that net name. | 10:36 |
tnt | Mmm, when looking at the .json I think the same internal wire has several names. But I'm not sure nextpnr can deal with multiple names per net ... | 10:46 |
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mithro | xobs: We should turn on the option which causes a missing clock constraint to be a fatal error | 19:43 |
mithro | xobs: I'm going to look at doing the 48MHz->12MHz transition on the rx right now | 19:44 |
mithro | I'm guessing you are probably asleep | 19:44 |
tnt | mithro: it's an error by default now. | 19:49 |
tnt | mithro: but one of the issue was that the clock constraint wasn't being applied | 19:50 |
mithro | tnt: ignoring clock constraints should cause a fatal error | 19:53 |
tnt | not an easy fix | 19:56 |
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