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| mithro | xobs: that is somewhat unexpected? | 01:15 |
|---|---|---|
| xobs | mithro: I've been working on getting epmem functioning. | 01:17 |
| mithro | Did it make sense how the pointers worked? | 01:24 |
| mithro | There where / are a couple of optimisations that I was planning on doing | 01:25 |
| xobs | I think I see how it's supposed to work, and yes. I think the big issue I'm running into now is DATA0/DATA1. But the good news is that I'm at a point where I'm starting to understand how this is all put together, which means I can start in on actually using it. | 01:25 |
| mithro | xobs: the DAT stuff it controlled by a seperate register | 01:29 |
| mithro | Be careful the simulation of registers is broken in some cases | 01:30 |
| mithro | Bblr | 01:30 |
| xobs | I noticed DAT was behaving a bit funny. I'd like to know how the simulation is broken. I can see the path forward, but I just need to understand the values of some of the registers. Things like eps_idx, which I'm still figuring out if it's a bitfield or a counter. | 01:42 |
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| mithro | xobs: it is neither | 05:31 |
| mithro | eps_idx is a mux select control | 05:31 |
| mithro | It selects which set of endpoint registers and such are used | 05:32 |
| mithro | ep_addr + IN/OUT | 05:33 |
| tannewt | mithro and xobs: I'm hoping to make it to teardown | 05:35 |
| mithro | tannewt: that would be great | 05:36 |
| tannewt | if either of you are ever in seattle let me know. I'm happy to meet up | 05:37 |
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| futarisIRCcloud | https://www.seeedstudio.com/Sipeed-TANG-PriMER-FPGA-Development-Board-p-2881.html | 22:46 |
| futarisIRCcloud | https://www.seeedstudio.com/Sipeed-MAix-Go-Suit-for-RISC-V-AI-IoT-p-2874.html | 22:46 |
| tpb | Title: Sipeed TANG PriMER FPGA Development Board - Seeed Studio (at www.seeedstudio.com) | 22:46 |
| tpb | Title: Sipeed MAix GO Suit for RISC-V AI+IoT - Seeed Studio (at www.seeedstudio.com) | 22:46 |
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