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| famubu[m] | Hi. I'm using yosys to synthesize a small design on to a gowin fpga (on sipeed tang nano 9K). | 13:44 |
|---|---|---|
| famubu[m] | Despite a lot of registers being available, yosys seems to use LUTs to make registers instead. | 13:44 |
| famubu[m] | Is there a way to indicate to yosys to use registers themselves if available and resort to making registers out of LUTs otherwise? | 13:44 |
| tnt | famubu[m]: wdym yosys is making registers out of luts ?!?! What makes you think that ? | 13:48 |
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| Adrien[m] | Latch implementation perhaps ? Intended register file in distributed logic ? | 14:57 |
| famubu[m] | I was checking the log made by yosys during synthesis. | 15:45 |
| famubu[m] | When I increase the size of the design, the LUT count goes up but FF count remains same. | 15:45 |
| famubu[m] | So I figured it's using LUT to implement registers. That was a guess. Am I wrong there? | 15:46 |
| famubu[m] | The 'printing statistics' part of the yosys log. | 15:46 |
| famubu[m] | Wait.. I might have been looking at the wrong log.. | 15:47 |
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