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| Adrien[m] | Hi Yosys developers, I'd like to remote a compilation difficulty. More exactly a re-compilation unnecessary burden | 08:41 |
|---|---|---|
| Adrien[m] | When I touch a file such as cells_map.v, and rerun make, there is a very heavy compilation done systematically that looks very unrelated | 08:42 |
| Adrien[m] | compilation of frontends/rtlil/rtlil_parser.tab.cc, frontends/rtlil/rtlil_parser.tab.cc | 08:42 |
| Adrien[m] | It takes several minutes and heavy on RAM, so this makes testing patches more difficult than it should. | 08:43 |
| Adrien[m] | I'm not familiar with lex'ing and the likes... is there something possible in Makefiles to avoid recompilation of these things ? | 08:44 |
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| whitequark[cis] | that sounds like an issue with your environment | 12:51 |
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| Adrien[m] | It is the package for Archlinux from the AUR (user repository, compile from sources). I'm just doing make to recompile. Even if nothing was changed, that piece of lengthy compilation is relaunched. It has always done that. | 19:02 |
| Adrien[m] | Maybe linked to the configure options used in the package ? | 19:02 |
| * Adrien[m] sent a code block: https://catircservices.org/_irc/v1/media/download/AeOf_sNFZ8cyfKn72J9bOU3wNI-qUbuksQYwun6YOphk9K5qA3DpyV21IGYtMn2xsalYUjUwH7pWJLkL-YmCKoy_8AAAAAAAAGNhdGlyY3NlcnZpY2VzLm9yZy9rc3lBZGNlb0FqUUtlb0Vmbkh6U3hmblM | 19:03 | |
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| Adrien[m] | Oh, veirder and weirder. If I touch the file `techlibs/xilinx/cells_map.v` or edit stuff in it that does not change whatever this ends up being processed to, then no lengthy recompilation happend. | 19:29 |
| Adrien[m] | But if meaningful content is touched, then the lengthy recompilation heppens. | 19:29 |
| Adrien[m] | So this seems intentional. | 19:31 |
| Adrien[m] | Is there really a dependency from techlibs/xilinx/cells_map.v to recompilation of frontends/rtlil/rtlil_parser.tab.cc, frontends/verilog/verilog_parser.tab.cc ? | 19:31 |
| Adrien[m] | Recompiling a parsing tool seems unnecessary. | 19:31 |
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