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| Guest2 | yop, I'm curious if yosys+nextpnr-ecp5 is able to use a block ram with output register configuration. I'm unfamiliar with those tool, but if I understand well the code here https://github.com/YosysHQ/yosys/blob/main/techlibs/ecp5/brams_map.v#L120 it seems that it's always inferred without output register? | 15:47 |
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| Adrien[m] | Hi all, does anyone have a declaration for primitive PS8 ? | 15:52 |
| Adrien[m] | Or a hint on where that can be found or generated | 15:52 |
| Guest2 | I have designed a riscv5 multi-stage, multi-hart as barrel processor. I'm using xiling vivado in parallel to crash-test my design. with vivado and targeting an xc7 or xcvu9p, adding an extra delay register after reading a block ram greatly improve timing. but with yosys for ecp5, it increase only slightly, and next-pnr both suggest that the bram | 15:53 |
| Guest2 | read registers are in the critical path. stuck at ~115MHz | 15:53 |
| Adrien[m] | vivado-generated wrappers are too much of a pain to manually process to get to a clear declaration... (vhdl preferred, but clear verilog would be great too) | 15:54 |
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| Adrien[m] | I was thinking maybe Yosys could have a sort of database of primitives, or taking it from prjxray, but it's not obvious | 16:12 |
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| Adrien[m] | granted, there are quite clear PS8 module declarations un Yosys repo, but ports are sorted by direction instead of by "channel", so more processing needed to reorder according to vivado-generated order, which is more human friendly. | 16:24 |
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| uis[m] | In what state xc7 pnr? | 16:43 |
| uis[m] | How hard and feature complete opensource design flow for zynq7? | 16:43 |
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| Adrien[m] | ok sed and grep will make it work eventually... | 17:04 |
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