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| vancz | Can I read somewhere about what kind of techniques are used to compile verilog to rtl? Specifically the uh...layer that implements whatever it is that is done to match the "procedural" verilog code to synthesized primizives? | 02:49 |
|---|---|---|
| vancz | primitives | 02:49 |
| vancz | In general, to satisfy my curiosity. | 02:50 |
| vancz | (and how this results in unintuitive synthesis insanity) | 02:53 |
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| whitequark[cis] | basically every vendor does their own thi g | 12:55 |
| whitequark[cis] | s/thi g/thing/ | 12:55 |
| whitequark[cis] | what yosys does is kind of some of the worst implementations I think | 12:55 |
| whitequark[cis] | just look at the recently filed memory init issue | 12:56 |
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| vancz | aw, yosys being the worst saddens me a bit | 16:27 |
| vancz | is there any theory on how it _should_ be done? | 16:29 |
| vancz | Is what Im asking about called the elaboration step? | 16:37 |
| jix | there's elaboration as defined by the system verilog spec and elaboration as used in (parts of?) the industry | 16:57 |
| jix | the former is just about resolving and instantiating a bunch of things | 16:57 |
| jix | but often people seem to mean that + turning it into a netlist using primitives corresponding to the used HDL operations (or synthesizable patterns) but what those primitves are would already differ between tools | 16:59 |
| jix | vancz: if you want to see a much cleaner verilog -> RTLIL frontend than yosys's read_verilog (which I agree is bad) you could look at https://github.com/povik/yosys-slang | 17:00 |
| jix | it uses an independently developed system verilog frontend that does what the standard calls elaboration and separately does the translation of precedural stuff to netlist primitives | 17:01 |
| jix | I haven't read too much of yosys-slang, but what I looked at was quite readable and made sense | 17:03 |
| vancz | for the moment im more interested in high level descriptions, i have enough on my plate than to try to reverse engineer another codebase (right now), thanks though! | 17:41 |
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| jix | one theoretical perspective of turning procedural hdl into netlists is to view it as symbolic interpretation | 18:09 |
| jix | it's a specific variant of it and there are some aspects that probably don't fit super well into that framework but I think that perspective can give a lot of useful intuition on how you'd even approach this | 18:09 |
| jix | the code you're interpreting is the procedural HDL and your symbolic value representation are netlists or operator DAGs or anything equivalent graph structured | 18:11 |
| jix | given the nature of HDLs and the retrofitted synthesis semantics, you also need to do some form of pattern matching for some synthesizable constructs and special case them (this is something where yosys's read_verilog does some things in the wrong order where it does some translation first and then pattern matches to detect things that shouldn't have been translated in that way...) | 18:14 |
| jix | uh and s/symbolic interpretation/symbolic execution/g | 18:16 |
| jix | there's also a somewhat related field of abstract interpretation which has some high level similarities to symbolic execution but the application of that would be for optimization and formal verification, not translation | 18:18 |
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| * vancz nods | 19:59 | |
| vancz | is it a thing for people to write hdl based on their own primitive library, and then retarget their model to different hardware by reimplementing the library | 20:02 |
| vancz | well, doing part of the synthesis tool's job manually basically | 20:02 |
| vancz | so idk, having a generic adder module and then for one target implementing a ripple carry adder and for another target using built in addition primitives, idk | 20:03 |
| jix | I haven't really seen that for generic logic like that, but for things that you don't want synthesis to mess with or don't trust synthesis to do the right thing with that's a thing that's done, can't tell how common it is though | 20:04 |
| jix | it seems super common to handle clock gating that way | 20:05 |
| vancz | whoops, wrong channel (hence the digression) but its fine | 20:06 |
| vancz | still relevant given synthesis i guess | 20:06 |
| vancz | thanks | 20:11 |
| vancz | hm. https://dl.acm.org/doi/pdf/10.1145/3622805 | 20:16 |
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