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famubu[m] | Any idea what I can try tweaking to get it right? I suppose it would be the constraints file? | 15:05 |
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famubu[m] | Well.. found at least one place where I goofed up. | 16:11 |
famubu[m] | The constraint file treated a 21-bit vector as a single bit. | 16:11 |
famubu[m] | So I modified to make 21 seperate mappings to pins: https://bpa.st/AZNQ | 16:11 |
tpb | Title: View paste AZNQ (at bpa.st) | 16:11 |
famubu[m] | I am not sure if all those pins are available to use as general IO. | 16:11 |
famubu[m] | Found the pin numbers from schematic at https://learn.lushaylabs.com/content/files/2022/08/Tang_Nano_9K_3672_schematic.pdf | 17:02 |
famubu[m] | Also tried gowin eda. That too is saying that frequency cannot be found. | 17:02 |
famubu[m] | Gowin eda tool said: 'No timing paths to get frequency of clk!' | 17:05 |
chipb | do you need to annotate your clock like https://github.com/YosysHQ/yosys/blob/main/examples/gowin/demo.sdc or something? | 17:22 |
chipb | I don’t know yosys, but “Info: Cell inp not found” seems a bit concerning to me. | 17:27 |
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