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| famubu[m] | Hi. I was trying to use nextpnr while targeting a gowin fpga (on a | 06:28 |
|---|---|---|
| famubu[m] | Sipeed Tang Nano 9K). | 06:28 |
| famubu[m] | The verilog code is autogenerated by an external tool over which I | 06:28 |
| famubu[m] | have no control. | 06:28 |
| famubu[m] | But nextpnr finishes its analysis quite fast (even while trying much | 06:28 |
| famubu[m] | larger designs). | 06:28 |
| famubu[m] | Each time, it finally gives this message: Info: No Fmax available; no interior timing paths found in design. | 06:28 |
| famubu[m] | The source verilog is not that understandable but it looks like there | 06:28 |
| famubu[m] | are registers involved. | 06:28 |
| famubu[m] | Does that mean that I have some misconfiguration? | 06:28 |
| famubu[m] | This is the source verilog: https://bpa.st/6P7Q | 06:28 |
| tpb | Title: View paste 6P7Q (at bpa.st) | 06:28 |
| famubu[m] | And this is the log file generated by the nextpnr-gowin command: https://bpa.st/SGCA | 06:28 |
| tpb | Title: View paste SGCA (at bpa.st) | 06:28 |
| famubu[m] | This is the constraints file that I'm using: https://bpa.st/EDGQ | 06:29 |
| tpb | Title: View paste EDGQ (at bpa.st) | 06:29 |
| famubu[m] | The yosys and nextpnr commands that I tried was: https://bpa.st/QNMA | 06:29 |
| tpb | Title: View paste QNMA (at bpa.st) | 06:29 |
| famubu[m] | Putting together all the paste links for convenience:... (full message at <https://catircservices.org/_irc/v1/media/download/ARHIyRCgJ5pDSEUPZTFTHIPP1a3OnjOQWKe-IHfJqIusCk4w-N5kRc6MnSk0yqlZ5vCNB58l3fqRzlp4CqCj3ze_8AAAAAAAAGNhdGlyY3NlcnZpY2VzLm9yZy9xcmx4Vk1tbk5wTndYVEdyZWxZWk1CTGg>) | 06:36 |
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| whitequark[cis] | that sounds like maybe a clock isn't connected properly | 23:15 |
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