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| Adrien[m] | Hi Guys, I've hit an issue with yosys techmap for Xilinx : | 09:32 |
|---|---|---|
| Adrien[m] | `/usr/bin/../share/yosys/xilinx/cells_map.v:151: ERROR: Signal `\A' with invalid width range -1!` | 09:32 |
| Adrien[m] | s/`\/'\\/, s/!`/!\`/ | 09:32 |
| Adrien[m] | I'm not sure this originates from my design or if it's a Yosys issue. | 09:34 |
| Adrien[m] | Is there a specific message to look for in Yosys log to get a candidate hint ? | 09:34 |
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| Adrien[m] | Next issue : Yosys plainly rejects designs that use task `$fatal` | 14:30 |
| Adrien[m] | (actually these occurrences are generated from ghdl from conversions of asserts) | 14:30 |
| Adrien[m] | Shouldn't these be just ignored instead ? | 14:30 |
| Adrien[m] | Yosys error message is : ERROR: Can't resolve task name '$fatal' | 14:31 |
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