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| juri_ | Is there an authoritative list of all of the nextpnr-XXXXXX projects, and what their current status is? | 16:11 |
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| lofty | juri_: no, but as a nextpnr dev I can give you one? :p | 17:32 |
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| juri_ | lofty: I'm currently looking to see if anyone is working on the spartan 6, virtex 4, or stratix 5. | 18:54 |
| juri_ | with a minor interest in the cyclone 4. | 18:55 |
| lofty | no, no, no, and no respectively | 18:55 |
| lofty | :p | 18:55 |
| juri_ | can i ask again, and get different answers? :) | 18:55 |
| lofty | If you ask about the cyclone v, perhaps? | 18:56 |
| juri_ | lost my bid on one of those. :) | 18:56 |
| lofty | Spartan 6/Virtex 4 requires xilinx ISE RE, which has been done, but nobody's contributed an architecture for those | 18:57 |
| juri_ | you wouldn't know anyone with an ISE 6.3 license they want rid of... :) | 18:57 |
| lofty | See, I'm nominally team lead of the cyclone v RE project | 18:58 |
| lofty | the iv is kind of out of scope because it's majorly different to the v | 18:58 |
| lofty | the stratix v... might be doable if we could source quartus standard | 18:59 |
| juri_ | I... am doing that. | 18:59 |
| juri_ | it's bloody expensive, but i'll get it done. | 18:59 |
| lofty | I mean, granted, nextpnr struggles with the Cyclone V for a number of reasons (do you want the long explanation or the short one...) | 19:00 |
| juri_ | the short one, because i don't have one of those on hand. | 19:01 |
| lofty | They're applicable to the stratix v too, I think | 19:02 |
| juri_ | then i am all ears. | 19:02 |
| lofty | There are two big reasons and a few smaller ones | 19:02 |
| lofty | One is to do with the timing information, one is to do with how LABs are laid out | 19:03 |
| lofty | Take your pick :p | 19:03 |
| lofty | juri_: ^ | 19:05 |
| juri_ | so, you're going to have torture with a max-length design for the timing, or... ? :) | 19:06 |
| lofty | Do you know what the SPICE simulator is? | 19:07 |
| juri_ | just barely. | 19:07 |
| juri_ | i've installed it (used to sysadmin at an engineering college) | 19:07 |
| juri_ | but as i was a sysadmin, and not a student.. grumble, grumble, destroycapitalism... | 19:08 |
| lofty | So, in normal, reasonable FPGAs, timing information is expressed as some inherent delay, plus a factor to express fanout delay | 19:08 |
| lofty | iCE40 doesn't even have the latter | 19:08 |
| lofty | But that would be reasonable, and this is an Intel/Altera FPGA, so instead timing information is expressed as a SPICE circuit and you need to propagate a waveform through all the elements in order to get your delays | 19:10 |
| lofty | Now, this is a pain, and so I have approximated the figures during routing, but that approximation leads to strange and weird behaviours like targeting a specific frequency, the router assuming it has met that frequency, and then final signoff timings says it failed | 19:11 |
| lofty | Or sometimes the opposite | 19:12 |
| lofty | (yes, this is what quartus_sta does) | 19:13 |
| juri_ | ok, that's super weird sounding, but also probably more accurate. | 19:14 |
| lofty | It probably is more accurate, yes | 19:15 |
| lofty | The other problem is that Altera are...far more confident in their tooling than we are, and so have designed the LABs accordingly | 19:16 |
| lofty | A Cyclone V LAB has 10 8-input ALMs, plus 4 LAB-wide control signals for things like enables and resets. | 19:17 |
| lofty | To feed all of this, there are 46 tile-dispatch muxes to source signals from global routing | 19:18 |
| lofty | ... You may notice the math doesn't quite add up here :p | 19:19 |
| juri_ | super fun. :) | 19:22 |
| juri_ | ok, i'll keep trying to acquire a reasonably priced (== my wife will not take my head highlander style) cyclone V. | 19:23 |
| lofty | Well, the two boards we use for testing are the Terasic DE10-Nano, and the Analogue Pocket | 19:25 |
| lofty | (why Analogue chose to send me a developer pocket I do not know, but I will not complain) | 19:26 |
| juri_ | good to know. I ended up with a DE0-nano. soooo close. :) | 19:29 |
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