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| Miyu-saki | Is there a way to enable like a strict mode since I keep accidentally assigning to registers, amongst other mistakes xd | 16:38 |
|---|---|---|
| lofty | Miyu-saki: it's called verilator :p | 17:23 |
| whitequark[cis] | or "not using verilog" | 17:37 |
| Miyu-saki | Oohh, I actually forgot about verilator. I've been using cxxrtl and since forgot that verilator does other things also. | 17:46 |
| Miyu-saki | As for not using verilog, what's a typical non-Verilog workflow that people use? | 17:46 |
| whitequark[cis] | https://amaranth-lang.org/docs/amaranth/latest/intro.html | 17:47 |
| tpb | Title: Introduction — Amaranth language & toolchain 0.5.0.dev304 documentation (at amaranth-lang.org) | 17:47 |
| Miyu-saki | I know there's that Python one and that Scala(?) one and that one which looks like Rust, but I'm not too familiar with them, nor how they'd interop | 17:47 |
| whitequark[cis] | https://amaranth-lang.org/play/ | 17:47 |
| tpb | Title: Play with Amaranth HDL! (at amaranth-lang.org) | 17:47 |
| Miyu-saki | Thanks! | 17:47 |
| whitequark[cis] | there's quite a few; Amaranth integrates with Yosys the closest (and soon with CXXRTL) | 17:48 |
| Miyu-saki | Thanks. :) I'll give it a try. Is it possible to import Amaranth(or well, the output) into a Verilog toplevel? | 17:52 |
| Miyu-saki | Ah sorry, I guess this one works: https://amaranth-lang.org/docs/amaranth/latest/start.html#converting-a-counter | 17:54 |
| tpb | Title: Getting started — Amaranth language & toolchain 0.5.0.dev304 documentation (at amaranth-lang.org) | 17:54 |
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| Guest7 | what is yosys' policy on the initial values of registers with no initial value defined in verilog? (just something like "reg [10:0] foo;") | 18:19 |
| Guest7 | from experimenting with it, it seems to assume it can be initialized to any value, usually it will be 0, unless the optimizer sees opportunities | 18:20 |
| Guest7 | I'm targeting ECP5 and can see that it generates TRELLIS_FF elements with REGSET values depending on the verilog init value | 18:34 |
| Guest7 | while we're at it, does anyone know how initialization/reset is supposed to work at all (with ECP5)? is there possibly an exemplary open source project using yosys that shows how it's done? | 18:36 |
| whitequark[cis] | Guest7: yes, 'x means the optimizer can do whatever it wants with the value | 18:37 |
| Guest7 | nice, very simple | 18:39 |
| Guest7 | someone somewhere claimed they were initialized by 0 by yosys, apparently that was wrong | 18:39 |
| whitequark[cis] | re: ECP5, you could look at https://github.com/amaranth-lang/amaranth/blob/main/amaranth/vendor/_lattice.py#L901-L994, which should cover nearly every Lattice FPGA | 18:39 |
| Guest7 | thanks, I'll check what verilog code it generates | 18:41 |
| Guest7 | what was this about Lattice tools ignoring register init values? is that still the case? for ECP5? | 18:41 |
| Guest7 | I saw some old posts that were sure about Lattice ignoring init values, but this could have been about ice only | 18:42 |
| lofty | Guest7: that's ice only, AFAIK | 18:51 |
| lofty | because of the different tooling used | 18:51 |
| Guest7 | thought so | 18:52 |
| lofty | iCE40 registers initialise to zero | 18:52 |
| lofty | ECP5 registers initialise to the reset value | 18:52 |
| lofty | <lofty> iCE40 registers initialise to zero <-- I think this is because the SiliconBlue engineers were ex-Altera, and Altera FPGAs also initialise to zero | 18:53 |
| Guest7 | the evil part is that the ice toolchain apparently ignores the verilog init values completely (no error or anything) | 18:54 |
| lofty | fortunately, we don't. though, if you ever decide to run synthesis with `-dff`, then for mapping reasons as many flops as possible will be converted to initialise to zero | 18:55 |
| Guest7 | is there a mode that initializes registers to random values, like verilator? | 19:05 |
| whitequark[cis] | not explicitly but you could do it yourself | 19:08 |
| whitequark[cis] | setattr -set init 0 w:* or something like that in your Yosys script | 19:08 |
| whitequark[cis] | re: iCE40 registers, this is not visible in the toolchain | 19:09 |
| whitequark[cis] | Yosys adds an inverter before and after the register to simulate initializing to 1 | 19:09 |
| whitequark[cis] | also, iCE40 isn't a Lattice FPGA; it's a SiliconBlue FPGA that was bought by Lattice | 19:09 |
| Guest7 | yeah I read the issue where wolf added support for ice reg init like that | 19:12 |
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| bjorkint0sh | SiliconBlue. that explains that. | 19:32 |
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