Friday, 2024-01-05

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ZevvWhat's the typical procedure to optimize my design for size, what's an efficient method of finding out where the luts are being used?18:51
loftyZevv: a good place to start is to use `-noflatten` to synthesise the logic hierarchically, which tells you which modules are contributing the most logic19:42
Zevvthanks, lemme check that19:47
Zevvright, that's nice19:49
Zevvgood. good. Is there a proper place on IRC to ask generic verilog questions? I'm past the total noob level I guess, but still have a lot to learn.20:04
loftyZevv: #fpga?20:28
loftysorry, ##fpga20:28
Zevvright, thanks. I checked #fpga but it was pretty empty20:28
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