Tuesday, 2023-12-05

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abraddUsing "prep; flatten; tribuf -formal" seems to resolve the error I was seeing01:20
abraddI noticed that when traces are generated they don't display the tristate port as 'z even when the input conditions mean they should01:21
abraddIs that expected or do I have some other issue?01:22
abraddI saw this in my own code, but started using https://gist.github.com/jix/6ccf5b58f10ce77cf40d9f13ed15db86 as a reference for testing. In it I also see that the tristate port goes to '0 instead of 'z when "en" is low01:23
jixthat's expected, the verification infrastructure doesn't actually support 'z so "tribuf -formal" converts it into equivalent logic + assertions to detect drive conflicts01:26
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abraddOk that makes sense. If I set any signal to 'z or it would otherwise have evaluated to 'z, is it always converted to '0 in the equivalent logic?03:16
abraddI've been testing the code at https://gist.github.com/jix/6ccf5b58f10ce77cf40d9f13ed15db86 and it behaves as expected given your description above, but I have another simple module that seems to be ignoring my "en" signal and I cannot figure out why03:17
abraddIt basically boils down to03:19
abraddassign tri_inout = en ? in : 1'bz;03:19
abraddassign out = tri_inout;03:19
abraddwith a formal verification section that runs a counter, counts to 3 and covers ( out == 1 && count == 3)03:19
abraddI can also provide the testcase if that is preferred03:19
abraddbut it seems the "en" is removed in the design.il file:03:20
abradd  connect \out \tri_inout03:20
abradd  connect \tri_inout \in03:20
abraddwhich is what I see if the traces, "out" goes high as soon as "in" does irrespective of "en"03:20
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