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| corecode | i wonder what this is about: | 17:28 |
|---|---|---|
| corecode | chip = pytrellis.Chip(dev_names[args.device]) | 17:28 |
| corecode | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ | 17:28 |
| corecode | RuntimeError: No such node (row_bias) | 17:28 |
| corecode | 17:28 | |
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| lofty | corecode: have you updated your prjtrellis-db? | 18:00 |
| lofty | That sounds to me like libtrellis and prjtrellis-db aren't in sync | 18:00 |
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| corecode | thanks | 19:46 |
| corecode | that might be it | 19:46 |
| corecode | i'm so confused why arch has prjtrellis in extra, but nextpnr is in aur | 19:47 |
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| xiretza[m] | there used to be a non-git nextpnr in the repos | 19:47 |
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| corecode | what happened? | 19:54 |
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| so-offish | Does yosys not support functions that return a real value? | 21:37 |
| so-offish | module func_real_test(); | 21:43 |
| so-offish | localparam real a_value = rpow2(10.0); | 21:43 |
| so-offish | function real rpow2; | 21:43 |
| so-offish | input real inval; | 21:43 |
| so-offish | rpow2 = inval * inval; | 21:43 |
| so-offish | endfunction // rpow2 | 21:43 |
| so-offish | 21:43 | |
| so-offish | 21:43 | |
| so-offish | initial begin | 21:43 |
| so-offish | $display("rpow2(10.0):%f",a_value); | 21:43 |
| so-offish | end | 21:43 |
| so-offish | endmodule | 21:43 |
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| jleightcap | is there a recommended method for distributing .ys scripts? | 23:22 |
| jleightcap | e.g. the same script with a different set of HDL input and -I dirs | 23:23 |
| jleightcap | rather than hard-coding inputs at the head of a `read_verilog` line | 23:23 |
| jleightcap | maybe best to just use TCL in this case, although i'm not familiar :-) | 23:24 |
| lofty | jleightcap: yosys scripts passed with `-s` are processed after files on the command line | 23:24 |
| lofty | so, instead of having `read_verilog` lines in your script, pass those files on the command line | 23:25 |
| jleightcap | ah yeah! that worked great, the only wrinkle i had was passing `-I` dirs for includes | 23:26 |
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| jleightcap | maybe like: `yosys -s synth.ys -p 'read_verilog -Ifoo $SRC'` | 23:28 |
| jleightcap | but the script processes before the -p command it seems | 23:28 |
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