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| keesj | Hi | 07:59 |
|---|---|---|
| keesj | I am trying to do timing accurate simulation using iverilog. It it possible using yosys to read liberty file and generate verilog containing the delay information? | 08:02 |
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| keesj | I am targetting sky130 | 08:03 |
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| gatecat | keesj: no, there's no ability inside yosys to deal with liberty timing (this is passed straight through to abc for synthesis) | 08:25 |
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| keesj | I have seen some behavioural verilog file that do contain timing. any idea on where to get some / how to convert somehow? | 08:50 |
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| keesj | So when yosys output the max frequency the device can run. What is this based on? | 08:55 |
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| gatecat | do you mean yosys or nextpnr? | 09:43 |
| gatecat | although yosys does have a sta command that can do this, it's not very widely used. it does indeed use the verilog timing information but that's very much fpga-oriented and was manually created, it can't load liberty timing | 09:44 |
| gatecat | for an asic flow you might get some delay information from the liberty printed by abc, but yosys isn't involved there other than telling abc where the liberty file is... | 09:44 |
| lofty | You'd want something like opensta for ASIC timing | 09:46 |
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