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| * knielsen found some numbers: 11 layers in IBM 90nm. 6 layers in intel 90nm, 9 layers in intel 90nm, 11/12 layers in TSMC 28nm | 07:02 | |
| Sarayan | metal layers or total layers? (there's the active and the polysilicon layer at the bottom) | 07:03 |
|---|---|---|
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| knielsen | I think metal layers | 07:03 |
| Sarayan | that doesn't seem insane | 07:03 |
| knielsen | The TSMC numbers are from https://www.techinsights.com/blog/review-tsmc-28-nm-process-technology ("layers of metal in the backend"), the other numbers are from the book "CMOS VLSI design" | 07:04 |
| tpb | Title: A Review of TSMC 28 nm Process Technology | TechInsights (at www.techinsights.com) | 07:04 |
| knielsen | Oh, typo, I meant "9 layers in Intel 45 nm" | 07:08 |
| knielsen | I'd assume that more advanced processes increase the number of layers. Or maybe there's a point of diminishing returns? | 07:09 |
| Sarayan | if you have more transistors you tend to need more routing, I guess | 07:13 |
| Sarayan | and perhaps since distances are less you can have more routing? | 07:14 |
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| singham | In all ICs, there is just the 1 semiconductor layer? | 18:51 |
| singham | base wafer? | 18:51 |
| knielsen | singham: That's the way they are produced. The transistors are created with the bottom layers, and then metal layers go on top with the routing | 18:52 |
| singham | There's no Y axis, sandwich type connections? | 18:52 |
| singham | knielsen: Yes, are you sure? Say there is Ryzen 3. They use a single layer 7nm process? | 18:53 |
| knielsen | there's vertical routing (called "vias"). And I think there's some instances where two (or more) individual chips are stacked on top of each other after wafer has been produced | 18:53 |
| singham | Aha. How probable is that? | 18:54 |
| singham | The stacking of wafers? Will there be say an AND gate on bottom layer, OR on above layer and connect both? | 18:55 |
| tnt | Well you have fancy process to stack multiple layers ( 3D NAND / X3D amd parts / ... ) but they're made in 2d and then stacked. | 18:55 |
| knielsen | singham: It's inherent in the process by which the wafer is produced. You start with the pure silicon crystal in a thin slice ("wafer"). Then regions are doped to create the N and P regions that form the mosfet transistors. Then the gate goes on top (or a bit more complex for finfet etc), and metal layers are layed down on top of that. The transistors can only be created on the bottom layer on the silicon | 18:56 |
| knielsen | crystal | 18:56 |
| singham | https://en.wikipedia.org/wiki/Three-dimensional_integrated_circuit | 18:58 |
| tpb | Title: Three-dimensional integrated circuit - Wikipedia (at en.wikipedia.org) | 18:58 |
| singham | Interesting | 18:59 |
| singham | Physical design is very complex compared to writing HDL | 18:59 |
| singham | There are sizes of gates, adding buffers, splitting of signals, cross-talking between wires, clock skews and jitters, and a lot more! | 19:00 |
| singham | knielsen: What do you do? | 19:08 |
| singham | I mean, what is your work? | 19:08 |
| singham | tnt and knielsen | 19:20 |
| singham | Thanks folks | 19:20 |
| * singham will see you comrades later | 19:20 | |
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| so-offish | Hey everybody - if I open up nextpnr, an I just run a command that's like, rip everything up and start over again? Like go back to unpacked, unplaced, unrouted? Or maybe just unplaced/unrouted would be good enough... | 23:30 |
| so-offish | I know "just look at the API" but I'm tired RN and if anybody just knows off the top of their head I'd appreciate it. | 23:30 |
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