Monday, 2023-02-27

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cr1901New Jersey, USA00:14
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singhamA small rookie question10:53
singhamIn SoCs, there are addresses like 0x004000 is for ram, 0x840000 if for uart, etc.10:54
singhamWhat does this exactly mean? These are connected by a bus I guess10:55
jnsingham: those are usually "physical" addresses on the memory bus connected to the CPU11:22
jnand when the CPU performs a load or store on address 0x4000, the bus interconnect will decode the address and forward the load/store to the RAM11:23
bl0xsingham: for a very simplistic example, you can take a look at step 17 of Bruno Levy's learnFpga course. This is about memory mapping peripherals in a soc. Look for isRAM and isIO signals.11:39
* singham is back11:50
singhamSo the pins are connected to adresses?11:51
singhamPhysical addresses are pins right?11:51
jnno, physical addresses (as the term is used in the context of CPUs) are not at all the same as pins on a chip11:56
jnthe word "physical" is in distinction to "virtual" addresses, that appear when you introduce an MMU11:57
singhamI think this must be a need since in unix, everything is a file so, everything must have to be mapped to a hex address?11:58
singhamSo say /dev/ttyS0 will be mapped to 0x005400 and all signals would be sent to that address?11:59
jnunix's file abstraction isn't really relevant to this, memory-mapped I/O exists without the concept of files11:59
jnfiles (including device files like /dev/ttyS0) are a software concept, MMIO addresses like 0x840000 are a hardware concept12:00
jnthe two things are connected throught the OS's UART driver, but not in a trivial way, there is some code involved12:01
singhamhmmmm, very interesting12:19
singhamSo a memory address may refer to either a portion of physical RAM, or instead to memory and registers of the I/O device.12:20
singhamThat is a fantastic statement from wiki of mmio12:21
singhamsolves many of my doubts12:21
singhamSo basically all memory elements of all devices are mapped to hex codes12:21
jnnot every bit of memory in every peripheral has to be mapped through MMIO, but other than that: yep12:26
jnand MMIO registers can act very different to RAM sometimes12:29
singhamSo the unmapped memory can be accessed with 0x00C000 + delta , right?12:29
jnsuch as only permitting reads, or only permitting writes, or not allowing to read back the value that was previously written12:30
jnsingham: what do you mean by unmapped memory?12:30
singhamYou said not every bit of memory in every peripheral has to be mapped12:31
singhamI was talking about the unmapped memory12:31
jnah. no, there's no general rule on how to access hidden memory12:31
jnit depends on the particular peripheral12:31
jnfor example, a UART might contain a FIFO with some memory to store incoming/outgoing characters, but you can't access the FIFO elements arbitrarily, you can only access the next element according to the First-In/First-Out discipline12:37
singhamSo just the last memory element of FIFO stack is mapped?12:41
singhamIn that case?12:41
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jnkind of, yes12:44
jn(the details of how a FIFO is often implemented, as a ring buffer, makes the "last element" a moving target though)12:45
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* singham thanks jn and bl0x for this great explanation.13:44
jnglad to help :)13:44
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bl0xYes, you're welcome. I'm also just at the beginning of my journey. Or so it seems with all the wondrous new things being made!13:53
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josuahhello! I am composing a .pcf for an upcoming dev board (FYI it has an RP2040 and an iCE40UP5k https://pico-ice.tinyvision.ai/ ).17:54
tpbTitle: pico-ice - pico-icepico-ice | An devboard featuring both an RP2040 and an iCE40SearchMenuExpandDocument(external link) (at pico-ice.tinyvision.ai)17:54
josuahIt uses PMODs for everything, I thought it could be nice to give pin names the PMOD names like PMOD1_SDA or PMOD0_MOSI or PMOD0_COPI etc.17:55
josuahBut doing so would clash in the .pcf, because of this: https://github.com/YosysHQ/nextpnr/blob/master/common/place/placer1.cc#L171 (also like that at other places)17:56
josuahany idea if there are flags to allow "aliases"? Or should it be done in verilog + vhdl + amaranth + ...17:56
josuahAn alternative would be having very long names including all the alternative signal names :P or simply let the user pick which section he is interested in to build its own PCF file17:57
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josuahhmm, I do not see anywhere in the PCF parser source some method to define aliases18:15
josuahI'll just offer users the data and let them copy-paste what they want in: low-tech high-flexibility!18:16
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gatecatjosuah: multiple references to the same pin in the pcf (with -nowarn so the unused ones don't cause problems) should be fine, so long as only one of them is actually used in the hdl design 19:10
gatecatdid you actually test that and hit that erorr or were you just speculating?19:10
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josuahgatecat: I encountered the error, but maybe I explained it wrong22:10
josuahshowing the actual situation might be best :) https://pico-ice.tinyvision.ai/pinout.html#pmod0-ice40-only22:11
tpbTitle: Pinout - pico-icePinout | pico-iceSearchMenuExpandDocument(external link) (at pico-ice.tinyvision.ai)22:11
josuahI will try to make a reproducer...22:11
josuahthank you for your answer!22:12
josuahoh wait that is right!22:12
josuahI was using multiple of them at once on the same top.v22:13
josuahthat is great news! \o/22:13
josuahI deduced a limitation from a bug on my side, sorry for the noise then!22:16
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so-offishHi everyone! Is there a way to pass -sv to synth_ecp5?23:16
so-offishNevermind I found a different way to do it23:26
so-offishDrop into yosys, read the file with the correct command, then do synth_ecp5 and use -run and coarse:json23:26
josuahat the step read_verilog -sv I guess, you were faster than me23:27
josuahoh wait ,that's not exactly what I thought23:27
josuahah yes "correct command"23:27
josuahthere is definitely more flexibility to yosys than I thought, quite the toolbox here23:30

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