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| bl0x_ | btw, is there any experience with the Cologne Chip FPGAs from Germany? They seem to use Yosys in their standard toolchain + a custom PnR. | 09:21 |
|---|---|---|
| trabucayre | bl0x_: https://github.com/trabucayre/GateMate_demos ? | 10:12 |
| trabucayre | last toolchain is a bit more stable | 10:17 |
| tnt | bl0x_: no experience yet, but according to UPS I should have a dev kit in a few hours :) | 10:43 |
| bl0x_ | tnt: what is the price for one? I requested a quote but no answer yet. | 10:50 |
| *** anuejn_ is now known as anuejn | 10:53 | |
| tnt | bl0x_: I have no idea sorry :/ | 10:55 |
| tnt | Ah nm, it's 234 EUR | 10:56 |
| tnt | it's on digikey. | 10:56 |
| tnt | search for CCGM1A1-E1-31B | 10:56 |
| trabucayre | bl0x_: I have to finish with https://github.com/YosysHQ/yosys/pull/3321 :-/ | 10:59 |
| trabucayre | tnt: you must replace ALL jumpers to avoid regulators issue | 11:01 |
| tnt | trabucayre: replace all jumpers ? | 11:12 |
| trabucayre | eval board has jumper like: https://www.technobotsonline.com/images/detailed/5/Ext-2700-070.jpg | 11:13 |
| trabucayre | I better to use something like: https://resources.altium.com/sites/default/files/inline-images/unnamed_3.png | 11:14 |
| trabucayre | to avoid reboot | 11:14 |
| bl0x_ | tnt: thanks | 13:03 |
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| dormito | Hmm. I just noticed that a recent (last ~ 14 days) sby (symbiyosys) seems to now be driving yosys incorrectly: get complaints that "formalff -setundef -clk2ff -ff2anyinit -hierarchy" has an unknown option. | 13:57 |
| jix_ | dormito: it should work with the latest yosys | 14:29 |
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| foxfromabyss | hi! I am currently using yosys to get systemverilog files elaborated and then fed into nextpnr for a xilinx board. That part works, even though I am using a couple of vendor specific primitives. However, as part of the design flow, I wanted to get `write_cxxrtl` to run. It sadly fails with `External blackbox cell `BUFGCE' is not marked as a CXXRTL | 22:05 |
| foxfromabyss | blackbox.`. I am at a loss as to how to configure a specific module to be blackboxed. I've tried to include the BUFGCE unisim source file from the vivado libs, but that didn't work. I am honestly at a loss at this stage and would appreciate any sort of pointers/directions :) | 22:05 |
| foxfromabyss | here's how I am invoking it: `yosys -q -L ${BUILDDIR}/yosys.log -m systemverilog -p "read_systemverilog -defer ${SOURCES}; read_systemverilog -link; hierarchy -top rvlab_fpga_top; synth_xilinx; write_cxxrtl test.cpp"` | 22:06 |
| foxfromabyss | here's how I am invoking it: `yosys -q -L ${BUILDDIR}/yosys.log -m systemverilog -p "read_systemverilog -defer ${SOURCES}; read_systemverilog -link; hierarchy -top fpga_top; synth_xilinx; write_cxxrtl test.cpp"` | 22:06 |
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