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| SeekerOfKnowlege | Hello I was wondering if yosys has support for all xilinx spartan 7 fpgas. Also where would the supported architectures be in the yosys documentation? | 04:54 |
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| lofty | Well, the seeker of knowledge will now never know | 05:23 |
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| pepijndevos[m] | Catherine: does this look like a yowasp, wasmtime, nextpnr, or apicula bug to you? https://github.com/YosysHQ/apicula/runs/7595136093?check_suite_focus=true#step:6:49677 | 10:23 |
| whitequark | will look in a few hours, ping me if i forget | 10:25 |
| pepijndevos[m] | <SeekerOfKnowlege> "Hello I was wondering if yosys..." <- relatedly... project x-ray isn't in the wiki yet https://github.com/YosysHQ/yosys/wiki/FPGA-family-feature-matrix/ | 10:31 |
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| ikskuh | heya! o/ | 16:58 |
| ikskuh | is there a example of how to use ecp5 IO primitives with yosys directly? instead of inferring them? such as open collector/push-pull/... | 16:59 |
| rowang077[m] | ikskuh: I'm not sure if they are inferred. I don't think so. | 19:41 |
| rowang077[m] | You can manually instantiate them using the primitive outlined in file:///home/rowan.goemans/Downloads/FPGALibrariesReferenceGuide33.pdf | 19:42 |
| rowang077[m] | Ah wrong link... | 19:45 |
| rowang077[m] | https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/FPGALibrariesReferenceGuide35.ashx?document_id=51084 | 19:45 |
| ikskuh | ah thanks <3 | 19:46 |
| ikskuh | i'll check it out | 19:46 |
| rowang077[m] | Example usage: https://github.com/lawrie/ulx3s_ql/blob/5a982274a1402dc8273799c5d8d76b6759086719/src/sdram.v#L100 | 19:46 |
| ikskuh | so what i wanna do is use the OBZ primitive | 19:48 |
| ikskuh | but how do i connect it to an output? | 19:48 |
| rowang077[m] | The OBZ primitive is not available for the ECP5 FPGA | 21:16 |
| rowang077[m] | ikskuh: See the Architectures supported. ECP5 has something similar though the BB primitive | 21:16 |
| rowang077[m] | Or BBPD/BBPU depending on your exact use case | 21:17 |
| rowang077[m] | Scratch that you are right this is available for the ECP5 | 21:18 |
| rowang077[m] | I was confused because I assumed bidrectionality. | 21:18 |
| rowang077[m] | Anyway what you want to do is instantiate the OBZ primitive connect O to the wire that maps to your FPGA output. Connect I to the driver and connect ~OutputEnable | 21:19 |
| rowang077[m] | to T | 21:19 |
| rowang077[m] | So the truth table in the document | 21:20 |
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