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| Sarayan | ikskuh: If you can use explicit i/o primitives with output and enable pins so that there is no Z involved | 00:16 |
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| mwk | ikskuh: the assign should work, tristates are supported enough for that pattern | 05:07 |
| mwk | the warning is kinda overzealous | 05:08 |
| mwk | I hope the pin is not literally named `output` though, that'd be a keyword | 05:08 |
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| jix | ikskuh: that pattern (a mux with one side being all-z) gets turned into a $tribuf cell by the tribuf pass, that pass gets run qutie early by synth_ecp5 (see help synth_ecp5 for the sub-passes it runs) | 10:02 |
| ikskuh | okay, cool | 10:02 |
| ikskuh | thanks | 10:02 |
| jix | ikskuh: so if it doesn't behave as expected, manually running the first few passes up to and including the tribuf pass and then looking at the output (using show) might help | 10:02 |
| jix | when using show you probably want to use a small test design though, otherwise it will just hang trying to layout a way to complex graph of the RTL | 10:03 |
| ikskuh | i found a better solution tho: i just pass-through the SPI through my FPGA instead of sharing the bus externally | 10:03 |
| jix | that sounds like it also makes debugging on the electronics/actual HW side easier :) | 10:06 |
| ikskuh | yep, exactly | 10:09 |
| ikskuh | it also allows me to maybe use that channel for other tasks later | 10:09 |
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