Sunday, 2022-05-29

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cr1901Oh I could've sworn you were already in this room, q3k :P15:08
q3kso did i15:09
cr1901When I switched to an IRC client w/ better autojoin, I stopped trying to keep all the rooms I'm in in my head. And it's only like 30 now15:10
cr1901(across 3 networks)15:10
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killjoytmux -> weechat -> znc ftw.17:16
killjoyI don't remember any channels I'm in, or networks, or passwords, or whatever.17:17
killjoyI'm apparently down to 59 buffer windows though. I think my highest number was in the 120's.17:17
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q3kanyway i'm here because i'm debugging some wierd behaviour when doing synth_ecp5 w/abc9: seems like when yosys parses the resulting AIG and renames cells to $lutfoo / $lutbar[baz], it attempts to rename two different cells to the same name, thereby triggering an assertion18:37
q3ki've got stuck attempting to understand what exactly the aiger frontend is doing and why, so i guess i should just file an issue for it? problem is, i can't seem to even minify my test case well enough, attempts at simplifying cause the issue to not manifest then18:38
q3kas in, this is what happens after adding some log() based debugging:18:39
q3kRenaming $lut$aiger244019$22639 to $lut\qf100_frontend.forkDMem_fifoReqRAMA_rv$port1__read[36]18:39
q3kRenaming $lut$aiger244019$26516 to $lut\qf100_frontend.forkDMem_fifoReqRAMA_rv$port1__read[36]18:39
q3ka naive interpretation of what happening is that abc emits two different LUTs with their Y (iiuc, output) ports connected to the same net, and since the LUTs get renamed based on their outputting net (?) the assert fires18:40
q3kbut that in turn implies that the netlist is junk, why would two LUTs have their outputs tied together?18:41
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corecodehi q3k 22:21

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