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| nonchip | hi, i'm trying to adapt this thing to my project (which uses verilog instead of GHDL): https://hackaday.io/project/180839-vhdlverilog-to-discrete-logic-flow but i noticed that there's no `SUBCKT` definition in my resulting spice netlist (the file literally starts with `X0` after a comment about the yosys version), and assuming that GHDL would have defined that somehow i'm wondering if/how i can instead tell yosys to emit that line? | 11:19 |
|---|---|---|
| tpb | Title: VHDL/Verilog to Discrete Logic Flow | Hackaday.io (at hackaday.io) | 11:19 |
| nonchip | alternatively, if anyone has suggestions for other "verilog to discrete logic" synthesis approaches i could try (apart from "draw by hand"), that would also be appreciated :) | 11:24 |
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| josuah | nonchip: you can generate a PDF diagram that can help | 15:03 |
| josuah | nonchip: but that is not a complete exhaustive diagram | 15:04 |
| josuah | nonchip: there are blocks with things that not exist "as-is" in gateware, like a multiplication, etc. | 15:04 |
| josuah | nonchip: so you would have to insert "discrete logic for basic block $x" here and there | 15:05 |
| nonchip | yeah i'm doing that currently, even fits rather readable on an A4 page since i ran `opt -full -purge -fine`, but yeah from there it's either print it out and draw on it, or i guess figure out some kinda techmap for turning things into mosfets :P | 15:05 |
| josuah | maybe the .dot files can be edited afterhand for this | 15:06 |
| nonchip | it's actually rather tame: a few tribufs, half of them are really just open drain pins, a few dff, a few mux, a few logic_*s | 15:06 |
| nonchip | and a few sections that are already ICs i know, wondering how to best optimize those away (e.g. i got a binary counter and a few registers that are currently being represented as various kinds of DFFs) | 15:07 |
| josuah | oh, actually use it with spice! I misread that at first | 15:08 |
| nonchip | i think that's possible with ABC and a custom techmap? | 15:08 |
| josuah | my knowledge of yosys toolchain might be lacking a bit to answer that though :S | 15:09 |
| nonchip | i just need essentially a "hey that bunch of cells is actually that IC over there" map file, shouldn't be too hard after i figure out *which* of the 50 million map functions to use :P | 15:10 |
| nonchip | my design (after optimization) fits on an A4 page, it's not too hard to write that map by hand really, but i'd rather then yosys give me something i can feed to e.g. kicad than actually plonking down all the chips by hand because i have rather wide parallel busses | 15:11 |
| josuah | oh, so it permits you to check if there is an ASIC matching the RTL design you need? | 15:11 |
| nonchip | i *think* that's what the ABC mapper is for but not 110% sure | 15:12 |
| nonchip | btw this is what i'm currently looking at if you're interested :) https://pdfhost.io/v/9eHP4whtd_opt | 15:13 |
| tpb | Title: opt.pdf | PDF Host (at pdfhost.io) | 15:13 |
| josuah | thank you! | 15:13 |
| nonchip | optionally replace all the `<16>`s by any bus width you might like, because it's flexible like that. it's a suuuper small and even suuuuuuperer dumb transport-triggered CPU core essentially. it literally just reads 2 addresses, copies from the first to the second, except if the second was 0, then it copies into the program counter (= jump) | 15:16 |
| josuah | nonchip: are you doing a discrete component processor? | 15:17 |
| nonchip | no ALU, conditional logic or anything else, it doesn't even read opcodes, literally just the arguments for the only thing it does: copying from/to 2 addresses. | 15:17 |
| nonchip | yup :) | 15:17 |
| nonchip | want to make an educational kinda "this is what you need to execute a thing" PCB with discrete components and lots of LEDs to view the bits in realtime, and any actual logic/maths/etc will just be hooked up as peripherals to the main bus in addition to presumably some memory. | 15:19 |
| nonchip | so essentially it's a 1-instruction-execute-cycle-on-a-board :P | 15:21 |
| nonchip | because technically that's all you need. add an ALU of your choosing on the bus, and just use that to overwrite the address of a jump target conditionally, and there's your turing completeness :P | 15:22 |
| josuah | this, on a room full of curious people, would likely get a lot of attention | 15:22 |
| josuah | that reminds me of the https://github.com/xoreaxeaxeax/movfuscator | 15:23 |
| josuah | a turing machine in a very small nutshell! | 15:23 |
| nonchip | yeah that was one inspiration for that | 15:24 |
| nonchip | fun fact my cpu can't even halt :P for that you need to either make a peripheral for control stuff like that (maybe also for selecting the clock speed or whatever), or jump into an endless loop :D | 15:26 |
| josuah | an ALU of your choosing on the bus | 15:27 |
| josuah | an ALU... as a peripheral! :D yay! | 15:27 |
| josuah | the principle of a microkernel, but for hardware | 15:28 |
| josuah | interesting | 15:28 |
| nonchip | i wonder if this cpu could also be implemented using a DMA controller with hardwired instructions... | 15:35 |
| josuah | is that not some sort of DMA already? | 15:44 |
| nonchip | essentially yeah | 15:44 |
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| jevinskie[m] | I share with you this gem https://github.com/jowinter/dmacu | 20:26 |
| jevinskie[m] | Minimal CPU Emulator Powered by the ARM PL080 DMA Controller. And it looks like they got nesting working :) | 20:27 |
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