Sunday, 2022-03-13

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Guest57i'm running `synth  -top $::env(DESIGN_NAME) {*}$::env(SYNTH_ARGS)` and crapping out at the abc step20:29
Guest57i've been trying to figure out how to recover the state that `synth  -top $::env(DESIGN_NAME) {*}$::env(SYNTH_ARGS) -noabc` induces20:29
Guest57so that i can restart the flow from just there20:29
Guest57but there's so much state in context and design and env variables and etc20:30
Guest57i tried `write_verilog/read_verilog` and `write_blif/read_blif` as checkpoints20:30
Guest57but that doesn't work either20:30
mithroPeople here might find this post interesting, from Xilinx's CTO - https://www.linkedin.com/pulse/chips-alliance-fpga-interchange-format-ivo-bolsens/?trackingId=D2msEW1%2FThmTehF86lCZ2Q%3D%3D20:55
tpbTitle: CHIPS Alliance FPGA Interchange Format (at www.linkedin.com)20:55
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