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| Guest30 | Hi everyone! Not sure if this is the right place for such questions, but anyway. I'm trying to figure out whether iCE40 is the right FPGA for my hobby project that involves ADC with 70-80 MHz serial bus, so obviously I need to do some nanosecond timing math... Does yosys/nextpnr-ice40 have some timing info for IO buffers? So far I only see that | 20:30 |
|---|---|---|
| Guest30 | nextpnr reports e.g. output pin critical path latencies between e.g. "posedge clk" and "...$sb_io.D_OUT_0 / D_OUT_1". Is there any (approximate) info on the delay between D_OUT_x and the actual hardware pin? Also would be curious to know the same for input side of things (delay, or ideally setup/hold requirements for a pin that registers input with | 20:30 |
| Guest30 | a DFF and puts it onto D_IN_x). Wasn't able to find this info in the datasheet. Most probably iCEcube2 could've helped there, but a.t.m I have neither the tool nor the license for it.. | 20:30 |
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| tnt | There is no IO timing info in the open toolchain at all. | 20:31 |
| tnt | Which iCE40 device are you considering ? | 20:32 |
| Guest30 | HX4K in TQFP144 package | 20:32 |
| tnt | HX will have 2.6~2.8 ns clock to out (from the internal clock edge to the moment it hits the externa IO). | 20:33 |
| tnt | It has 1.0~1.4 ns setup time on IOFF input (relative to the internal clock edge) | 20:35 |
| Guest30 | Hm.. Thanks for the numbers :-) Where did you get that data, iCEcube2? | 20:35 |
| tnt | And ~ -500 ns hold time (negative hold time) again, against the internal clock edge. | 20:36 |
| tnt | yes, from icecube 2, made some test veriog, wrote down the numbers. | 20:36 |
| mwk | umm... units? | 20:36 |
| tnt | oh sorry, -0.5 ns ... | 20:37 |
| tnt | (I wrote it down in ps ...) | 20:37 |
| mwk | yeah, microsecond-order IO timings would be obviously wrong | 20:38 |
| mwk | ~unless you're dealing with insane FPGA such as UltraScale~ | 20:38 |
| mwk | ~hrm | 20:38 |
| tnt | Guest30: It's long winder and I ramble a lot but I got through an example there https://www.youtube.com/watch?v=mitAhMOt3zI for flash timing (fast SPI) | 20:39 |
| tnt | you can probably skip the first 30 min or so. | 20:40 |
| Guest30 | tnt ok, thanks, will check | 20:44 |
| Guest30 | BTW, I could've searched first through the git before asking... there seems to be a timing DB in icestorm: https://github.com/YosysHQ/icestorm/blob/master/icefuzz/timings_hx8k.txt . Next to it is timings.py script which can convert it to HTML format. And it lists e.g. IO, PRE_IO cells with PACKAGEPIN wires, so I guess I can look into there if I | 20:47 |
| Guest30 | need more info :-) | 20:47 |
| Guest30 | But I guess nextpnr just does not use / show all the data from it. | 20:47 |
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| Guest30 | Wow. The difference between registered and unregistered output latency is impressive. Registered output will have 309ps for glbclk->OUTCLK + 140ps for OUTCLK->PADOUT (output ff) + 2353ps for PADOUT->PACKAGEPIN (output buffer), 2802ps in total from clk to pin (matches quite well with 2.6~2.8ns number above, I took worst-case numbers from the | 21:23 |
| Guest30 | timings). OTOH, unregistered output will have 2237ps for DOUT0->PADOUT + 2353ps for PADOUT->PACKAGEPIN, 4590 ps in total, and this not including all the routing needed to get the signal on DOUT0. | 21:23 |
| Guest30 | This confirms my occasional thought that if you want to output internal FPGA _clock_ onto the pin, and you want minimal skew, it's better use registered DDR output instead of casually routing clock through the fabric to DOUT0/1 and then running it straight to the pin without FFs. | 21:23 |
| mwk | that's pretty much the standard procedure for doing this | 21:24 |
| mwk | for source-synchronous applications | 21:24 |
| Guest30 | ok, didn't know that :-) (I'm just beginning with FPGAs) | 21:25 |
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| tnt | yeah, it's not even a choice unless you work at trivially slow speeds. | 21:42 |
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