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| sagar_acharya | When I open Makefile of picorv32 in an editor, things crash, has anyone else experienced this? | 08:56 |
|---|---|---|
| sagar_acharya | I have to kill the process with "kill -9 <pid>". I just deleted the repo, cloned it and again with fresh downloaded file, featherpad goes in an infinite loop | 08:58 |
| sagar_acharya | Doesn't happen with nano, strange! | 08:59 |
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| sagar_acharya | What does picosoc contain in addition to rv32 processor? In layman terms. | 09:32 |
| tnt | https://github.com/YosysHQ/picorv32/tree/master/picosoc ... like ... first picture of the readme. | 09:34 |
| sagar_acharya | Alright, I still find it difficult to understand the working. Say I have ps2 and vga, where would they be connected? | 09:38 |
| sagar_acharya | I guess VGA would be on GPIO controller | 09:38 |
| tnt | Huh no. | 09:39 |
| Sarayan | I wonder if I could run that in the mister using the sdram as ram and the usb-serial as serial to probe internal stuff. I don't have working bram yet | 09:39 |
| Sarayan | or possibly the ddr3 as ram. Do we have scripting languages implementations on the rv32 that would allow for such probing? | 09:39 |
| sagar_acharya | Ok, I'll read a bit on this basic nomenclature and be back | 09:40 |
| Sarayan | sagar: it does flash and serial, no vga or ps2 with the provided code | 09:40 |
| sagar_acharya | Yes, I'm saying if I want to use vga and ps2, I should be able to connect it in "Your circuit" part. | 09:41 |
| Sarayan | sure | 09:41 |
| Sarayan | in the "Memory mapped user peripherals" | 09:42 |
| Sarayan | you have to decide where you put the framebuffer though for vga | 09:42 |
| Sarayan | and what it looks like | 09:42 |
| Sarayan | and how you ensure that the scanout and the cpu accesses don't walk on each other | 09:43 |
| Sarayan | all the usual hardware fun | 09:43 |
| sagar_acharya | I'm new man. The things usual for you are new to me. | 09:44 |
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| sagar_acharya | I started with verilog a week ago. I have done digital electronics though. I understand signals, fsms, karnaugh maps, and completed a course of vlsi | 09:45 |
| sagar_acharya | Where the prof implemented rv32 processor in a 5 stage pipeline at end. | 09:45 |
| sagar_acharya | I'm unaware of typical hardware debugging. | 09:46 |
| sagar_acharya | 0x03000000 .. 0xFFFFFFFF | 09:46 |
| sagar_acharya | This is address range of memory mapped peripherals. | 09:46 |
| sagar_acharya | Do these hex codes point to particular connection lines, after all, I have to connect vga and ps2 to some lines. | 09:47 |
| Sarayan | https://github.com/YosysHQ/picorv32/blob/master/picosoc/picosoc.v | 09:51 |
| Sarayan | you can see the (minimalist) memory decode at 117+ | 09:51 |
| Sarayan | 03xxxxxx is indicative, you can do what you want in reality | 09:51 |
| sagar_acharya | Thanks, that's interesting! I'll be back after some study of pre-requisites. | 09:53 |
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| sagar_acharya | I read on UART and XIP SPI Flash controller. What's their role in picosoc. I guess UART is used for inputs. I didn't get what XIP SPI Flash controller would do. | 16:19 |
| sagar_acharya | I didn't get storage of instruction addresses in XIP instead of instructions themselves. Would the instruction addresses point to SRAM? | 16:19 |
| sagar_acharya | How would the control of picosoc look like? Say I attach ps2 and vga and nothing else, just picosoc as in uart, sram, picorv32 and xip. How would the connections happen and how would control flow happen? | 16:21 |
| gatecat | no, the instructions are stored as-is in flash - XIP means that the 16MB (max) of SPI flash is directly mapped to memory and code in SPI flash can be run by the processor by pointing the PC into that range | 16:23 |
| sagar_acharya | alright. So control inputs for loading the instructions to rv32 are not shown in the diagram? | 16:24 |
| gatecat | no, they're loaded on the system bus | 16:25 |
| gatecat | picorv32 doesn't have a split instruction/data bus | 16:25 |
| gatecat | everything is loaded on the same bus | 16:25 |
| sagar_acharya | I mean that bus is shared across uart, sram and xip so, there must be some control right where other 2 would stop while 1 is using the bus? | 16:27 |
| gatecat | that's the decode Sarayan has pointed to | 16:27 |
| sagar_acharya | aah ok. | 16:28 |
| sagar_acharya | nice | 16:28 |
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| sagar_acharya | Can you tell me about 8 inputs except system clock and reset | 16:29 |
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| sagar_acharya | This nomenclature is really tough for me. I'll try reading some verilog of picosoc. | 16:34 |
| sagar_acharya | If someone knows some basic book for understanding basic structure of such SoC, please recommend me. | 16:34 |
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| sagar_acharya | For iCE40, are there already available SoCs with ps2 and vga support? | 17:58 |
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