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| sagar_acharya | https://github.com/AndresNavarro82/vt52-fpga/blob/main/video_generator.v | 18:13 |
|---|---|---|
| sagar_acharya | I need small help. I'm unable to determine what pin to set in pcf file for output reg video in above verilog file. | 18:14 |
| sagar_acharya | For hsync and vsync, there is DPIO pin type with bank 3. | 18:15 |
| sagar_acharya | What is PIO and DPIO? | 18:17 |
| sagar_acharya | What is bank? For now, I merely translate using pinout sheet | 18:18 |
| Sarayan | what's your hardware? That code seems to be generating a monochrome digital signal | 18:19 |
| sagar_acharya | hx8k olimex board | 18:20 |
| sagar_acharya | iCE40 | 18:20 |
| Sarayan | iCE40-IO board for vga? | 18:20 |
| sagar_acharya | yes | 18:21 |
| sagar_acharya | What pins to assign? What is DPIO and PIO? | 18:21 |
| sagar_acharya | What is bank? | 18:22 |
| Sarayan | https://raw.githubusercontent.com/OLIMEX/iCE40-IO/master/ICE40-IO_Rev_A.pdf | 18:23 |
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| Sarayan | video should go to all nine VGA_{RED,GREEN,BLUE}[1-3] | 18:24 |
| Sarayan | https://github.com/OLIMEX/iCE40HX1K-EVB/blob/master/demo/ice40-io-video/ice40-io-video.pcf | 18:24 |
| Sarayan | that pcf could be quite useful | 18:24 |
| Sarayan | also, it seems according to that github that your have a 100MHz clock input available | 18:25 |
| Sarayan | D usualy means differential, but it tends to be a mode, not a requirement | 18:26 |
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| xiretza[m] | Sarayan: that's a different board | 18:27 |
| xiretza[m] | and a different FPGA | 18:27 |
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| xiretza[m] | this is the one for the HX8K: https://github.com/OLIMEX/iCE40HX8K-EVB/blob/master/demo/ice40-io-video/ice40-io-video.pcf | 18:34 |
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| xiretza[m] | doesn't match up at all with what's in https://github.com/AndresNavarro82/vt52-fpga/blob/main/vt52.pcf though | 18:35 |
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