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| ikskuh | it's very incomplete support | 07:16 |
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| Xark | ikskuh: Yes, in my experience it is incomplete, but still quite useful to improve base Verilog language use. I found I can use many nice synthizeable sv features (like enum), but with a few restrictions (that had reasonable work-arounds). I had to find a SV "subset" in my project that would work with Verilator, yosys and iVerilog. :) | 21:34 |
| Sarayan | iirc yosys is mostly missing prototypes in headers and non-packed structures? | 21:35 |
| Xark | Sounds about right. I think fairly recently some "fancier" features were implemented (and some nice fixes). :) | 21:40 |
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