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| Guest85 | I met a problem when using Yosys to synthesis a verilog file. In a verilog module I declared a parameter, say parameter MIN = 4. Then, I synthesis it, and I got a correct results. However, when I overwrite the parameter outside the module with the same value (defparam mod.MIN = 4;), and redo the synthesis, the results is wrong. I believe this is | 22:04 |
|---|---|---|
| Guest85 | the only change. Don't know why this could happen | 22:04 |
| Guest85 | I need to change the parameter, can someone help to solve this myth? | 22:07 |
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