| *** tpb <[email protected]> has joined #yosys | 00:00 | |
| *** gsmecher <[email protected]> has quit IRC (Ping timeout: 268 seconds) | 00:28 | |
| *** strobo <[email protected]> has quit IRC (Ping timeout: 260 seconds) | 02:04 | |
| *** strobo <[email protected]> has joined #yosys | 02:06 | |
| *** bpye <bpye!~bpye@user/bpye> has quit IRC (Quit: Ping timeout (120 seconds)) | 02:16 | |
| *** bpye <bpye!~bpye@user/bpye> has joined #yosys | 02:17 | |
| *** scientes_ <[email protected]> has joined #yosys | 02:29 | |
| *** scientes <[email protected]> has quit IRC (Ping timeout: 260 seconds) | 02:30 | |
| *** kbeckmann <[email protected]> has quit IRC (Ping timeout: 260 seconds) | 02:39 | |
| *** kbeckmann <[email protected]> has joined #yosys | 02:49 | |
| *** piegames <[email protected]> has quit IRC (Ping timeout: 256 seconds) | 02:58 | |
| *** piegames <[email protected]> has joined #yosys | 02:58 | |
| *** strobo <[email protected]> has quit IRC (Ping timeout: 256 seconds) | 02:59 | |
| *** strobo <[email protected]> has joined #yosys | 03:00 | |
| *** cr1901 <cr1901!~William@2601:8d:8600:911:109:c768:abb5:da22> has joined #yosys | 03:26 | |
| *** emeb_mac <[email protected]> has quit IRC (Quit: Leaving.) | 06:01 | |
| *** peepsalot <peepsalot!~peepsalot@openscad/peepsalot> has quit IRC (Ping timeout: 260 seconds) | 06:04 | |
| *** peepsalot <peepsalot!~peepsalot@openscad/peepsalot> has joined #yosys | 06:19 | |
| *** kristianpaul <kristianpaul!~paul@user/kristianpaul> has quit IRC (Read error: Connection reset by peer) | 07:02 | |
| *** kristianpaul <kristianpaul!~paul@user/kristianpaul> has joined #yosys | 07:07 | |
| *** FabM <FabM!~FabM@2a03:d604:103:600:f72a:7fad:83ca:f34e> has joined #yosys | 07:20 | |
| *** dlobato <[email protected]> has joined #yosys | 09:05 | |
| *** dlobato <[email protected]> has quit IRC (Remote host closed the connection) | 09:14 | |
| *** vidbina <vidbina!~vid@2a02:3032:4:58:4f9c:8db4:bcbc:ae82> has joined #yosys | 09:54 | |
| *** vidbina <vidbina!~vid@2a02:3032:4:58:4f9c:8db4:bcbc:ae82> has quit IRC (Remote host closed the connection) | 10:29 | |
| *** vidbina <vidbina!~vid@2a02:3032:4:58:da94:edcb:94d4:abb0> has joined #yosys | 10:30 | |
| *** vidbina <vidbina!~vid@2a02:3032:4:58:da94:edcb:94d4:abb0> has quit IRC (Ping timeout: 260 seconds) | 10:54 | |
| *** vidbina <[email protected]> has joined #yosys | 12:12 | |
| *** gsmecher <[email protected]> has joined #yosys | 12:14 | |
| *** unkraut <[email protected]> has quit IRC (Ping timeout: 246 seconds) | 12:26 | |
| *** unkraut <[email protected]> has joined #yosys | 12:26 | |
| lambda | woah, someone sure greased the release machine :D | 12:29 |
|---|---|---|
| FL4SHK | lambda: what do you mean? | 12:33 |
| lambda | FL4SHK: only a little over three months between releases? that's quite a nice change of pace after the >2y gap between 0.9 and 0.10 | 12:35 |
| mwk | we basically decided to do monthly releases from now on | 12:37 |
| mwk | we're not *quite* there yet with the infrastructure and processes for that, but we're getting there | 12:37 |
| lambda | awesome | 12:37 |
| FL4SHK | lambda: I see | 12:39 |
| FL4SHK | Does yosys support SV classes as namespaces? | 12:39 |
| FL4SHK | I heard yosys supports more of SV now | 12:39 |
| FL4SHK | That's one thing I generally don't expect synthesis of SV to support, but at the same time, it's how the SV standard mentions to do type generics with structs and subprograms. | 12:40 |
| FL4SHK | such that you can do `my_class #(.member_t(int))::my_struct_t` | 12:41 |
| FL4SHK | I normally use nMigen for synthesizable code, and I may be continuing that. | 12:43 |
| mwk | nope, there is no support for classes at all | 12:48 |
| mwk | it's not even recognized as a keyword from what I see | 12:48 |
| FL4SHK | That's unfortunate | 13:01 |
| FL4SHK | sv2v it is if I get back into SV | 13:01 |
| FL4SHK | For the record | 13:01 |
| FL4SHK | I'm not referring to use of classes directly, just as namespaces | 13:01 |
| mwk | there is a new verilog frontend planned, but uhh it's kind of not the highest priority right now | 13:02 |
| FL4SHK | like packages, but with the power to parameterize them | 13:02 |
| mwk | yeah, I know | 13:02 |
| FL4SHK | Cool | 13:02 |
| mwk | I'm unfortunately a little too familiar with SystemVerilog | 13:02 |
| FL4SHK | I haven't written much SV lately | 13:02 |
| FL4SHK | nMigen seems like it's able to do every high level thing I'm interested in | 13:02 |
| FL4SHK | if combined with the extensions to nMigen that I wrote | 13:03 |
| mwk | yeah, it is quite great | 13:03 |
| FL4SHK | OH, you're in #nmigen as well, derp | 13:04 |
| *** vidbina <[email protected]> has quit IRC (Ping timeout: 268 seconds) | 13:12 | |
| *** gsmecher <[email protected]> has quit IRC (Ping timeout: 268 seconds) | 14:13 | |
| *** FabM <FabM!~FabM@armadeus/team/FabM> has quit IRC (Ping timeout: 268 seconds) | 15:37 | |
| *** gsmecher <[email protected]> has joined #yosys | 15:45 | |
| *** FabM <FabM!~FabM@2a03:d604:103:600:58e:6c56:130f:ec6d> has joined #yosys | 15:49 | |
| *** vidbina <[email protected]> has joined #yosys | 16:13 | |
| cr1901 | *Homer "New Billboard Day" voice*: New yosys release! | 16:41 |
| *** Kamilion <Kamilion!kamilion@user/kamilion> has quit IRC (Read error: Connection reset by peer) | 16:44 | |
| *** Kamilion|ZNC <Kamilion|[email protected]> has joined #yosys | 16:45 | |
| *** FabM <FabM!~FabM@armadeus/team/FabM> has quit IRC (Quit: Leaving) | 16:46 | |
| *** Kamilion|ZNC is now known as Kamilion | 16:48 | |
| *** emeb <[email protected]> has joined #yosys | 17:33 | |
| *** vidbina <[email protected]> has quit IRC (Ping timeout: 260 seconds) | 18:00 | |
| cr1901 | https://github.com/YosysHQ/yosys/pull/3070 Well I'm a bit stuck... taking a break. Mr. Nextpnr's Wild Ride is almost at an end for now | 18:01 |
| gatecat | cr1901: you need a call to `techmap` to turn the `$not` into a `$_NOT_` before abc | 18:07 |
| gatecat | abc only works on the gate-level cells | 18:07 |
| *** emeb_mac <[email protected]> has joined #yosys | 19:02 | |
| *** somlo <[email protected]> has quit IRC (Remote host closed the connection) | 19:05 | |
| *** dys <dys!~dys@user/dys> has quit IRC (Ping timeout: 260 seconds) | 19:23 | |
| *** ec <ec!~ec@gateway/tor-sasl/ec> has joined #yosys | 19:39 | |
| cr1901 | gatecat: Okay, you are correct, and my patch as-is is wrong. I didn't notice this was happening because nextpnr doesn't error on unknown cells if --pack-only is specified, just warns that it wasn't placed. | 19:51 |
| cr1901 | I don't like my solution at all. I wish iopadmap supported active-low tristates, but Idk how to add that functionality (nor do I know whether it would be accepted since it's feature creep) | 19:52 |
| *** dys <dys!~dys@user/dys> has joined #yosys | 20:19 | |
| mwk | cr1901: wrt your tribuf pull request, I think it's time I did something about neg-polarity tristates properly | 20:41 |
| mwk | ie. I'd like to cook a proper solution soon-ish and avoid multiple synth passes dealing with the same problem in completely different ways | 20:42 |
| mwk | maybe a whole iopadmap refactor would be appropriate, hmm | 20:43 |
| mwk | > I don't like my solution at all. I wish iopadmap supported active-low tristates | 20:43 |
| mwk | oh yes, it should | 20:43 |
| mwk | it's not fully obvious to me yet whether it's the right place to put *all* handling, there may be merit in splitting the "polarity decision" and "IO pad mapping" parts into two passes | 20:44 |
| mwk | but we definitely need better support | 20:44 |
| mwk | and generic support | 20:44 |
| cr1901 | Fine, I'll hold off then and let you do your thing. I'm not begging for tristate support yet for my designs. If I truly need it, I can do *points to the shit in my PR* manually. | 20:45 |
| cr1901 | I mainly added this to test part of my nextpnr PR (I'll make that now), but I'm satisfied the nextpnr functionality works and I don't _need_ my yosys PR merged. | 20:46 |
| mwk | mhm, right | 20:46 |
| cr1901 | Honestly, makes me feel a lot better to hold off for now :P | 20:46 |
| mwk | so | 20:49 |
| mwk | you need the inverter extracted before the LUT mapping happens | 20:50 |
| mwk | and, if the inverter happens to be $not, before techmapping happens | 20:50 |
| mwk | a simple solution to your problems is to just move iopadmap early enough in the script, like synth_xilinx does | 20:50 |
| mwk | there's no reason why pad mapping should happen *late*, after all | 20:51 |
| cr1901 | I do not have a particular reason why it's done late. Probably more "don't touch it, lest I break something". But it's already broke. So that'll work. | 20:51 |
| mwk | yeah, you copied from one of the passes that does it late because the target uses an active-high enable | 20:52 |
| mwk | synth_xilinx is different because it needs active-low enable | 20:52 |
| mwk | but really, it should just be done early everywhere for consistency | 20:52 |
| mwk | ... anyway | 20:52 |
| mwk | I think a better solution would be to enhance the cell library a bit | 20:53 |
| mwk | have both active-high and active-low versions of the $_TBUF_ / $tribuf cells | 20:53 |
| mwk | and, like for FFs, have a pass that legalizes tribuf cells to be either all-positive or all-negative | 20:54 |
| mwk | and then iopadmap's job would be simplified because it can always expect tribuf cells of the right polarity already and can happen as late as you'd like | 20:54 |
| mwk | while the tribuf-legalize pass could be somewhere earlier | 20:55 |
| mwk | that also gives us a target-independent active-low tribuf cell, which IMO is nice | 20:55 |
| cr1901 | Maybe I'd add a new-section called "legalize" between "flatten" and "coarse" | 20:55 |
| mwk | no | 20:55 |
| cr1901 | Would it go w/ "map_ios" then? | 20:56 |
| mwk | you already have a conceptually similar dfflegalize call, don't you? | 20:57 |
| mwk | I think they belong together | 20:57 |
| cr1901 | yea, I call that the "map_ffs" pass | 20:57 |
| cr1901 | err map_ffs section* | 20:57 |
| cr1901 | I can't tell you what past-me was thinking other than "yes I did copy from synth_ecp5 most likely and pared it down to what I need" | 20:58 |
| mwk | whitequark: do you have any opinions on the above? | 20:58 |
| whitequark | nothing that bears mentioning | 21:00 |
| cr1901 | Cool, I'm finishing up my nextpnr PR | 21:04 |
| *** kraiskil <[email protected]> has joined #yosys | 21:05 | |
| mwk | whitequark: ack | 21:05 |
| *** vidbina <[email protected]> has joined #yosys | 21:09 | |
| cr1901 | "tribuflegalize" is the solution I like best, FWIW. It'll pair well w/ dfflegalize and generate gate-level cells before abc has had a chance to run. It might even enable me to remove the iopadmap mess completely and techmap directly to FACADE_IO (we'll see...) | 21:11 |
| *** kraiskil <[email protected]> has quit IRC (Ping timeout: 256 seconds) | 21:11 | |
| mwk | you'd still need to map the plain I/O buffers, no? | 21:11 |
| *** kraiskil <[email protected]> has joined #yosys | 21:12 | |
| cr1901 | Maybe, I thought I could map _TBUF_ to FACADE_IO directly | 21:13 |
| cr1901 | I'll have to actually look and see and not just think out loud :P | 21:13 |
| cr1901 | nextpnr PR opened. And with that, barring any fixups, Mr. Nextpnr's Wild Ride has come to an end for now | 21:15 |
| *** kraiskil <[email protected]> has quit IRC (Ping timeout: 268 seconds) | 21:21 | |
| mwk | it's a little trickier than that | 21:22 |
| mwk | there's a reason why the bidirectional I/O pad cells have *4* pins, not *3* like a tribuf | 21:22 |
| mwk | that's an important bit that iopadmap takes care of | 21:23 |
| cr1901 | Ahh | 21:23 |
| *** Niklas[m] <Niklas[m]!~nsmlzlmat@2001:470:69fc:105::c93a> has quit IRC (Ping timeout: 246 seconds) | 21:26 | |
| *** whitequark <whitequark!~whitequar@2001:470:69fc:105::37> has quit IRC (Ping timeout: 246 seconds) | 21:26 | |
| *** adamgreig <[email protected]> has joined #yosys | 21:27 | |
| *** agg <[email protected]> has quit IRC (Ping timeout: 246 seconds) | 21:27 | |
| *** bq <[email protected]> has quit IRC (Ping timeout: 268 seconds) | 21:28 | |
| *** smkz <smkz!~x@user/smkz> has quit IRC (Ping timeout: 264 seconds) | 21:28 | |
| *** bq <[email protected]> has joined #yosys | 21:28 | |
| *** Niklas[m] <Niklas[m]!~nsmlzlmat@2001:470:69fc:105::c93a> has joined #yosys | 21:30 | |
| *** smkz <smkz!~x@user/smkz> has joined #yosys | 21:31 | |
| *** whitequark <whitequark!~whitequar@2001:470:69fc:105::37> has joined #yosys | 21:39 | |
| *** adamgreig is now known as agg | 21:43 | |
| *** gsmecher <[email protected]> has quit IRC (Ping timeout: 264 seconds) | 21:52 | |
| *** kristianpaul <kristianpaul!~paul@user/kristianpaul> has quit IRC (Ping timeout: 264 seconds) | 22:13 | |
| *** V <[email protected]> has quit IRC (Ping timeout: 264 seconds) | 22:17 | |
| *** V <[email protected]> has joined #yosys | 22:17 | |
| *** emeb <[email protected]> has quit IRC (Quit: Leaving.) | 22:39 | |
| *** somlo <[email protected]> has joined #yosys | 22:58 | |
| *** kristianpaul <kristianpaul!~paul@user/kristianpaul> has joined #yosys | 22:58 | |
| *** philtom is now known as philtor | 23:10 | |
| *** ec <ec!~ec@gateway/tor-sasl/ec> has quit IRC (Remote host closed the connection) | 23:25 | |
| *** ec <ec!~ec@gateway/tor-sasl/ec> has joined #yosys | 23:26 | |
| *** vidbina <[email protected]> has quit IRC (Ping timeout: 268 seconds) | 23:33 | |
Generated by irclog2html.py 2.17.2 by Marius Gedminas - find it at https://mg.pov.lt/irclog2html/!