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| chipb | cr1901: SV is a rather generic synthesis language, right? I guess theoretically, on some exotic target library, it might not need to be FFed. suppose your delay could be fulfilled by unclocked propagation? | 00:33 |
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| chipb | in all practicality, thinking of it that way is probably silly though. :-P | 00:33 |
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| piegames | chipb: https://github.com/Redcrafter/verilog2factorio https://github.com/itsFrank/MinecraftHDL | 09:31 |
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