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| b2xiao | gatecat: re your comment on my PR - tbh I don't completely understand what OFX0/1 are | 23:43 |
|---|---|---|
| b2xiao | my understanding is that there's a fixed connection from OFX0 to F5A (and a fixed connection from OFX1 to FXA), which are presumably meaningful in LOGIC mode when it's possible to select F0 to come from OFX0 via F5A or F0 (and F1 from OFX1, likewise) | 23:44 |
| b2xiao | but I guess in CCU2 mode the outputs are fixed to F0/F1 (of the slice) and cannot be changed, is that right? | 23:45 |
| piegames | Are there any issues when manually implementing $past in hardware instead of using the built-in? | 23:48 |
| piegames | (Contex: https://symbiyosys.readthedocs.io/en/latest/verilog.html) | 23:48 |
| piegames | *t | 23:48 |
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