Tuesday, 2019-12-10

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meawopplgreeting humans02:05
meawopplanyone around in here?02:05
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meawopplanyone alive?02:40
meawopplI am looking for some help with nextpnr, does this channel do that?02:40
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meawopplWhen I get assertion failures in nextpnr, is this the place to talk about them?03:20
soreareither here or ##openfpga03:45
sorearbut if you can’t stay online for more than 50 minutes you may have better luck with email or github issues03:47
sorearidk who else is awake at this hour03:47
ZipCPUAt least the channel is recorded, so there is a chance he might see that someone responded to him03:53
meawopplI'll give it a go tomorrow AM when i reboot into linux again, until then i am stuck with the windows toolchain :/03:53
sorearNearly certain nextpnr supports Windows04:28
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meawopplso, if I am having an assertion fault in nextpnr, what do I share to reproduce it?  a .json and the flags I used?14:27
meawopplI basically seem to seg-fault nextpnr anytime I use a module with parameters14:27
ZirconiumXWhat are you using to synthesise for nextpnr? Yosys, right?14:29
meawopplyosys, yes14:29
ZirconiumXGiven that using a module with parameters is amongst the most common Verilog operation, I suspect it's not the problem here14:30
ZirconiumXThe JSON, the assertion error, that command lines of both Yosys and Nextpnr and possibly the input HDL14:31
meawopplgotcha, I will reboot into linux land in a bit post those here14:32
meawopplthey are specifically related to the ice40 builtin modules (tristate buffers and led driver) if that helps any14:33
ZirconiumXNot as such14:33
whitequarkare your nextpnr and yosys up-to-date?14:34
meawopplyeah, I built both from source this week14:34
meawopplI also made a .deb for nextpnr, and I am tempted to roll a ppa for all these tools to make them apt friendy14:35
meawopplaiit, power-cycling to linux, brb14:38
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meawopplheyo, I got caught in windows update land :/14:52
meawopplaiiit, so I am invoking yosys as the following:14:53
meawoppl`yosys -s integrate.ys`14:53
meawopplthe script has only a few lines:14:53
meawoppl`read_verilog source/impl_1/*.vsynth_ice40 -top top -blif magicschoolbus.blifwrite_json magicschoolbus.json`14:54
meawopplbah, that is getting munged:14:54
meawoppl`read_verilog source/impl_1/*.v`14:54
meawoppl`synth_ice40 -top top -blif magicschoolbus.blif`14:54
meawoppl`write_json magicschoolbus.json`14:54
meawopplthat is all ^^14:55
meawopplwhen I run nextpnr I call the following:14:55
meawoppl`nextpnr-ice40 --up5k --package sg48 --json magicschoolbus.json --pcf pins.pcf --asc output.asc`14:56
meawopplthe output looks like this:14:56
ZirconiumXmeawoppl: Why not just `yosys -p "synth_ice40 -top top -json magicschoolbus.json" source/impl_1/*.v`?14:57
tpbTitle: nextpnr bug? · GitHub (at gist.github.com)14:57
ZirconiumXThat seems a bit simpler :P14:57
meawopplyeah that is better14:58
ZirconiumXdaveshah: ^14:58
whitequarkcan you show the code?14:58
daveshahYeah this is obviously a bug14:58
meawopplwhitequark I don't think I can share it without stripping a bunch of material15:01
meawopplthe observation I wanted to put forward is that if I take the parameters out of the ice40 modules the pnr call succeeds, which I find interesting15:01
daveshahNo one will fix it without the code15:02
meawopplkk, let me try to make a minimal repro15:02
meawoppleta ... 5 or so?15:05
meawopplalso, thanks!15:05
meawopplalright, that was much easier than I thought to strip down15:10
meawopplmaking it 1-command reproduction15:10
tpbTitle: GitHub - meawoppl/nextpnr-bug-repro: Not much to this all (at github.com)15:17
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meawoppldaveshah, if you clone the above and run `reproduce.sh` it should show the problem I am having15:18
daveshahHaving a look now15:19
daveshahmeawoppl: https://github.com/meawoppl/nextpnr-bug-repro/blob/master/LedController.v#L39-L42 should be strings like "0b1"15:20
tpbTitle: nextpnr-bug-repro/LedController.v at master · meawoppl/nextpnr-bug-repro · GitHub (at github.com)15:20
daveshahthis is silly but it is for compatibility with the Lattice tools15:20
daveshahlet me add a better error though15:20
meawopploh, are parameter literals treated strangely somehow?15:23
daveshahthis is very specific to the UltraPlus primitives15:23
daveshahthe SiliconBlue era primitives (LUTs, RAMs, SB_IO, PLLs) don't do this - only the LED driver and UltraPlus hard IPs do15:24
meawopplgotcha, howabout the high-freq osc?15:24
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daveshahthat's string style too15:25
meawopplwoah, I think it all just worked.....15:31
meawopplthanks so much daveshah15:31
meawopplhow can I contribute to this project?  It is going to save me a ton of time I can already tell15:31
daveshahmeawoppl: first step is to keep the issue reports coming :) (I've just improved the error message in this case)15:32
daveshahalso have a look at open Yosys/nextpnr issues15:32
daveshahhi corecode!15:32
corecodehi dave15:32
corecodeyou coming to congress this year?15:32
daveshahno, I won't be15:32
corecodelast year there were a lot of people doing icebreaker tutorials15:33
meawopplis that the one in Munich?15:33
corecodeare there any ultra bugs that need attention?15:34
daveshahNot sure, I have not tried the ultra support myself15:34
corecodei am using it15:34
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meawoppldaveshah, one other question if you have some bandwidth15:41
meawopplwhat is the right way to do a bidirectional pin (read and write) where the "high" needs to be high-impedance? (already has external pullup)15:43
corecodeinstantiate a pin gpio instance and change OE15:44
daveshahWhat you have looks alright to me15:44
daveshahoh yeah, you can just have the output data set to 1'b0 as corecode15:45
daveshahI did this for I2C a while ago15:46
tpbTitle: MARLANN/cameraif.v at master · SymbioticEDA/MARLANN · GitHub (at github.com)15:46
corecodeyep looks like what i suggested15:48
corecodewould be nice if you could express this in verilog and reliably get the right IO instantiated15:48
meawopplcorecode and daveshah thanks for the leads15:56
meawopplcan I keep pestering this channel with veriolog questions?15:56
corecodei guess15:58
corecodethere is also ##verilog and ##fpga15:58
ZirconiumXAlso ##openfpga16:07
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steeeelsHi all, I have rather silly question and tbh it's more verilator related one, but still. Could anyone tell me if there's something wrong with this piece of code: https://pastebin.com/w6fWKUfa The reason I'm asking is that it works 100% fine if I pass --public option to verilator and doesn't work w/o it.17:31
tpbTitle: [VeriLog] module lfsr_rnd #( parameter POLY = 32'h80200003 ) ( input wire - Pastebin.com (at pastebin.com)17:31
whitequarkseems fine to me. how does it break?17:32
steeeelsIn case I run verilator w/o --public option, every signal is zero, except POLY of course, please check these screenshots: https://imgur.com/a/A3hZtJo17:35
tpbTitle: Imgur: The magic of the Internet (at imgur.com)17:35
steeeelsThe generated c++ code by verilator looks more or less similar, at least for those signals. It's hard to tell for sure for 10k lines of code17:39
whitequarkit generates 10kloc for that one module?17:42
steeeelsNope. The SoC generates 10k LOC, but the issue is with lfsr module.17:44
whitequarkare you sure there is a problem in lfsr module and not something else?17:45
whitequarkit might be visible in the lfsr module but have its cause elsewhere17:45
steeeelsI believe so, yes. At least the code executes unless it tries to read something non-zero from random generator, which in this case is impossible. I'll try to minimize the reproduction and create a topic on veripool17:48
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