Wednesday, 2019-11-27

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develonepi3Hello all Has anyone tried to use docker, to build yosys tools (archne-pnr, icestorm, yosys and nextpnr), for raspberry pi or for Ubuntu?16:08
ZirconiumXdevelonepi3: I think everything builds natively.16:19
ZirconiumXThough, don't use arachne-pnr anymore; nextpnr is superior.16:19
develonepi3Zirconiumx: Yes, I have built on both Rpi3B+ & Rpi4B but it still takes a long time.  Was just wondering since I have older versions of nextpnr.16:24
ZirconiumXdevelonepi3: Are you using HeAP or SA?16:28
ZirconiumXdevelonepi3: It's a very memory-intensive build because it's creating binary blob databases containing all the routing information it needs16:29
develonepi3Zirconiumx: Don't think so.16:30
ZirconiumX`nextpnr-ecp5 --help` should say what the default choice is for `--placer`.16:31
develonepi3Zirconiumx: I am using nextpnr-ice40, no --placer option fairly old. Last update in Aug 4.16:49
ZirconiumXdevelonepi3: Definitely update it, then.16:50
ZirconiumXPlus, consider that place and route is a slow operation anyway.16:51
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tntIs it possible after doing a 'read' of all the input files to get yosys to write a single file that contains all it needs to pursue the synth without neededing any other files ?  Goal is to real all sources (including any includes and init files for memories) on one machine, then ship that file to a build server that will do most of the work and just spit out the resulting .json.17:41
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daveshahtnt: that is the aim of -E18:03
daveshahI don't know if it handles init files correctly18:03
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whitequark-E seems orthogonal18:25
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whitequarkI think doing read;hierarchy;write_ilang would work?18:25
tntYeah reading the description of -E it seems like it would just list all the files rather than make a single file containing everything.18:30
tntwhitequark: the ilang only contains a bunch of modules with "attribute \src "misc/xclk_strobe.v:36"" pointing to the actual sources :/18:31
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tntOh wait, seems hierarchy needs the -top option to really do anything and then it might do what I want.18:34
tntI need to add read_verilog -D_ABC -lib +/ecp5/cells_sim.v +/ecp5/cells_bb.v  as well for all the blackbox, but that might work.18:34
whitequarktnt: yep, need -top or -auto-top18:37
whitequarkthe \src attribute is purely for debug info18:37
whitequarkyosys never reads those paths18:37
tntNot sure mem init are handled properly though :/18:41
whitequarkthey are18:42
whitequarkthere is no way to read an external init file from rtlil18:42
whitequarkwhich is actually kind of unfortunate18:43
tntOh yeah, I see indeed they are my bad.18:43
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janrinzedoes nextpnr / yosys slice large memory into dp16kd per bit or does it do it 'wide'? i noticed that larger memory has a big amount of muxes..22:13
tntit tries different things22:13
tntin the yosys output log you'll see the different config/layout it considered and the score it attributed to each and why it picked the one it did.22:14
janrinzeI can use a block of 64Kx16 made of dp16kd at 140 MHz but the same amount with reg [15:0] memory[0:65535] will max out at 70 Mhz..22:15
ZirconiumXUnfortunately memory_bram sucks.22:19
ZirconiumXThis is one of the reasons why: at present it has no concept of RAM speeds.22:20
janrinzeI'm trying to get my head wrapped around how the reg [15:0] memory[0:65535] gets converted to dp16kd. The code in nextpnr looks pretty obscure to me (forgive me my ignorance.)22:22
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ZirconiumXjanrinze: the conversion is done in Yosys22:29
ZirconiumXIn memory_bram22:29
daveshahYosys does tend to prefer bit slicing large RAMs22:30
daveshahThis should improve timing as it reduces the need for read decode muxes22:30
janrinzedaveshah: that's precisely what i hoped. Unfortunately in the timing analysis I see that is has around 9 muxes. When using bit slicing it would only need 3, i.i.r.c.22:44
janrinze64K can be done with 4xDP16KD per bit. Since we have 4bit LUT it will require 3 LUT to select the correct output bit.22:46
tntlook at the yosys output log ...22:50
tntthat might give a clue22:50
tntIt definitely picks 16k x 1 geometry, but there is still a lot of LUTs. Probably the semantic of DP16K doesn't perfectly match what it wants and it needs a bunhc of external logic ...22:58
tntOne of the reason I don't like inference. How do I express _i_don_t_care_ how r/w conflict are handled for instance ?22:58
janrinzeyes, it does pick 16kx1. but a lot of glue around it apparently.22:59
ZirconiumXjanrinze: do the two sides of your RAM use different clocks?23:00
janrinzetnt: when both reading and writing is clocked then it's easy to use DP16KD23:00
janrinzeZirconiumX: In the VGA I use DP16KD directly since it doesn't require any init values. Also the VGA side is read-only.23:02
janrinzefor the CPU i like to setup memory so it will run the bootloader or bare metal code out-of-the-box.23:03
tntinterestingly 32kx16 looks fine. but 64kx16 the lut goes from 21 to 139 ...23:07
janrinzehmm.. perhaps i should try to split it in two 32 KB blocks :D23:10
janrinzeeehhr.. 32kx16 blocks x2 of course.23:10
tntFirst thing it generates  a CE signal independently for each RAM which is useless, it doesn't matter if the CE of the 'unused' RAM is enabled.23:20
tntAnd then the 4:1 MUX structure is ... insane.23:21
tntThat's what it uses to mux the output of 4 RAM into the output bit ...23:23
daveshahYes, the problem is that ABC can't use the slice mux structures properly23:25
tnt-nowidelut seems to "fix" it23:27
daveshahParticularly with ABC9 in a real design this will only be a big problem if the structure is on the critical path23:29
daveshahOtherwise it will likely be relaxed23:29
daveshahIt also seems like the CE issue could be improved in memory_bram by registering the address MSBs rather than the decoded signals23:32
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janrinzedaveshah: that's exactly how i use it with the VGA memory. The latched address MSBs are used to select the appropriate bit for reading.23:39
tntJust tried -nowidelut on the supercon badge design. Hurts timing a bit it seems (on the super representative sample of 3 seeds ...) but reduces the pnr time by 15% and the slice count by 10%.23:40
daveshahYes, nowidelut is effectively an area/timing tradeoff23:47
ZirconiumXI've been wondering about nowidelut on the Cyclone V. Since it's natively a LUT6 without being able to mux it higher, what would it even do?23:51
ZirconiumXThere's the option of using LUT4s only, of which two can be packed into an ALM. Guess I'd have to conduct experiments23:56

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