Tuesday, 2019-11-12

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promachERROR: timing analysis failed due to presence of combinatorial loops, incomplete specification of timing ports, etc.01:27
promachyosys does not give me loop warnings01:27
promachso, what really causes this error ?01:27
promachok, found what causes the error :)01:41
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pepijndevosHow can I tell yosys not to do assign {foo, bar, baz} = {a, b, c}?11:03
pepijndevosI did splitnets but it still uses some arrays11:04
pepijndevosIt's actually doing assign { gen_043_, gen_042_, gen_041_, gen_040_, gen_039_, gen_038_, gen_037_, gen_036_ } = { \ctr[25] , \ctr[24] , \ctr[23] , \ctr[22] , \ctr[21] , \ctr[20] , \ctr[19] , \ctr[18]  };11:05
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ZirconiumXpepijndevos: But why? This is, after all, entirely valid Verilog semantics11:19
pepijndevosZirconiumX, but not Verilog that the Gowin floorplanner understands.11:20
pepijndevosIt only deals with a very limited subset of post-synth Verilog11:20
ZirconiumXHmm, write_verilog stuff like this might be one for whitequark?11:22
daveshahThis is a known issue, see https://github.com/YosysHQ/yosys/issues/128611:23
tpbTitle: Yosys emits assigns with a concatenated expression on the LHS · Issue #1286 · YosysHQ/yosys · GitHub (at github.com)11:23
daveshahUnfortunately structural Verilog isn't well defined11:23
ZirconiumXSo yeah, have fun pepijndevos11:33
pepijndevosI love fun11:35
cr1901_modernIssue #1286 came up in omigen... ISTR that this is _not_ valid Verilog12:02
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daveshahcr1901_modern: it definitely is12:28
daveshahsee https://usercontent.irccloud-cdn.com/file/IiMjT1Jq/Screenshot%20from%202019-11-12%2012-28-00.png12:28
daveshah(from 1364-2005 p70)12:29
daveshahthe question is whether it is "valid" structural Verilog, but I don't think structural Verilog is actually a defined thing12:29
cr1901_modernthat's the sysverilog spec?12:31
daveshahNo, Verilog 200512:31
daveshahI don't think it's a new feature12:31
daveshahlet me check 0112:31
cr1901_modernOkay, I'm wrong then. Well, ISE doesn't accept that either12:31
daveshahYeah, same example appears in 2001 too12:32
daveshahI'm surprised by that, it's quite a common pattern12:32
cr1901_modernThat being said, note that your example is {a, b} = c + d + e;12:34
cr1901_modernISE doesn't accept {a, b} = {c, d};12:34
cr1901_moderni.e. I think the destructuring on both sides is what it doesn't like12:34
daveshahThat's even stranger12:34
ZirconiumXmwk: Why on earth did you decide to reverse engineer such a cursed compiler?12:35
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FSM_DudeHey! Is there anyway here who develops/runs Yosys on a MacBook?12:51
daveshahIt's definitely something some people do, don't think any of the core devs use macos though12:54
FSM_DudeOkay! I'm running into a problem since I updated Xcode / MacOS12:55
FSM_DudeI just ran make clean, and rebuilding everything to see if it might solve the issue12:55
ZirconiumXAt risk of being snarky, it's difficult to help solve "problems"12:58
FSM_DudeI understand! I actually wanted to ask for help, then thought: maybe cleaning and rebuilding helps12:59
ZirconiumXSure, but we still don't know what your problem is13:00
FSM_DudeIf the problem persists, I'll let you guys know, and give a somewhat broader explanation what exactly goes wrong :)13:00
FSM_DudeWell, basically, when I ran fsm_recode -encoding binary, I get a Thread_Bad_Access13:01
FSM_Dudeand then Yosys stops13:01
ZirconiumXThis is already a lot more helpful13:01
ZirconiumXCan you post your code somewhere?13:02
daveshahIf you don't get to the bottom of it quickly, running with valgrind (if that exists on osx) is often handy for this kind of thing13:02
ZirconiumXI think Valgrind has support for OS X13:02
FSM_DudeCool, Ill look into it!13:05
FSM_DudeAfter rebuilding it still happens13:05
FSM_DudeI didn't change any code here13:06
daveshahIt's possible that some latent bug has been triggered by a compiler/stdlib update13:06
ZirconiumXIt wouldn't be the first bug we've had with fsm.13:08
FSM_DudeThe Thread_Bad_Access seems to happen in register.cc13:10
FSM_Dudein Pass::call(RTLIL::Design *design, std::vector<std::string> args)13:10
FSM_DudeI'm fairly new to C++ and Yosys, so sorry for need being of great help...13:10
ZirconiumXWhich line?13:10
ZirconiumXIt'll say something like "register.cc:XXX"13:11
mwkZirconiumX: well if it wasn't that cursed, I could perhaps actually use it instead of reversing it13:12
ZirconiumX...You have a point13:12
FSM_Dudeline number 294 : pass_register[args[0]]->execute(args, design);13:13
FSM_DudeFor now I guess, Ill switch to my linux machine :P13:14
mwkFSM_Dude: could you give us the verilog / ilang code that triggers the bug?13:15
FSM_DudeCan I post it all here?13:16
FSM_DudeOr how do I get the Verilog to you guys13:16
ZirconiumXCopy and paste it to gist.github.com13:17
ZirconiumXDon't paste it into IRC; it will be very spammy and difficult to use13:17
FSM_DudeMind you, it's not my verilog code. Im a student trying to run a set of verilog benchmarks. I'm interested in building new state encoding techniques into Yosys and analyse the outcomes13:20
FSM_DudeTo analyse, I use a set of benchmark verilog files :)13:20
ZirconiumXSure, but anything that takes in Verilog is inevitably going to crash somewhere13:22
FSM_DudeIt's a shiftreg I think13:22
FSM_DudeI gtg now, Im on my laptop gonna get to my linux machine at home13:23
ZirconiumX...It works under WSL13:24
ZirconiumXWindows Subsystem for Linux13:24
FSM_Dudethe fsm_recode -encoding binary?13:25
FSM_DudeGuess it's Xcode/OSx specific?13:25
ZirconiumXWhat's your full Yosys command line?13:25
FSM_DudeThanks for testing tho! I'll switch to linux then13:25
ZirconiumXSadly we can't fix the bug if you do13:25
FSM_DudeThats what I run13:27
FSM_Dudein the Yosys shell13:27
ZirconiumXThat script works too13:30
FSM_DudeBefore I updated my OSx and Xcode everything worked. So I guess it has to do with that change13:30
ZirconiumXPossibly. That still suggests there's a latent bug *somewhere*13:30
FSM_DudeHow can I investigate this better/be of help to you guys13:32
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ZirconiumXFunnily enough, Yosys has a command for finding bugs13:33
ZirconiumXSo, I presume you have that script in a file somewhere?13:33
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FSM_DudeI type every command in the shell most of the times13:34
ZirconiumXYou should put it in a script13:34
ZirconiumXAnd then use `yosys -s script.ys`13:34
FSM_DudeOkay, thanks!13:35
ZirconiumXDoes that still crash with the segfault?13:35
ZirconiumXRight, so now I want you to run `yosys -p "bugpoint -clean -script script.ys; write_ilang testcase.il" your_verilog_file.v`13:39
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FSM_Dudeautoidx 313:43
FSM_Dudeis in both .il files13:43
FSM_DudeI gtg now, got classes. I'll come back to you! Let's try to fix it :)13:44
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