Monday, 2019-11-11

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promachHave anyone used before ?08:24
tpbTitle: GitHub - FPGAwars/apio: Open source ecosystem for open FPGA boards (at
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pepijndevoswelp Warning: Failed to find a route for arc 20 of net clk.08:25
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whitequarkjanrinze: yosys does not currently have TDP RAM support08:28
whitequarkinference support*08:28
pepijndevosI probably have a typo or a missing pip somewhere, I think??08:42
pepijndevos(using the generic backend to PnR stuff)08:42
pepijndevosIt seems somehow that the clock wire doesn't have the right pips to connect all the way.08:42
daveshahThere are some ifdefs in the router you can enable (combined with --debug) to see what it is trying08:48
pepijndevosOh ok, I'll have a look08:49
pepijndevosIs there also a way to dump the internal routing graph? I suppose it might be a bit big to comprehend08:52
daveshahNo, although in the past I've usually used python scripts to poke the routing graph08:53
pepijndevosdaveshah, can you somehow get an interactive console into nextpnr, or you have to write the poking in --pre-pack over and over?09:04
daveshahthe only interactive console is in the gui09:04
daveshahcode.interact() in a script might also work09:06
daveshahBut I haven't tried the latter09:06
pepijndevosHm, does the gui work with generic?09:07
pepijndevosI tried good old pdb.set_trace() but that just hangs without getting a prompt09:08
daveshahJust tried and code.interact() seems to work09:08
daveshahNot sure about gui, I think there were some issues with the generic prepack scripts09:09
pepijndevosWhere do you put that? NameError: name 'code' is not defined09:09
daveshahneed an import code too09:09
daveshahsomething is needed for ctx to work properly too; let me see09:10
daveshahso these two lines are what you want09:11
daveshahimport code09:11
pepijndevosbtw, this is the output with --debug, have not looked into it much further
tpbTitle: Ubuntu Pastebin (at
daveshahFor routing graph debugging you probably want to uncomment some of the ifdefs in the router too to see what it visits along the way09:14
pepijndevosyea, will do that after I'm done poking at the Python api09:16
promachhow do I create a pcf pins (clock and reset) declaration file for ice40 architecture ?09:32
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daveshahpromach: have a look at
tpbTitle: nextpnr/ at master · YosysHQ/nextpnr · GitHub (at
daveshahand examples like
tpbTitle: icebreaker-examples/icebreaker.pcf at master · icebreaker-fpga/icebreaker-examples · GitHub (at
promachthanks daveshah09:42
pepijndevosYea, seems like there is no pip on the IOB output -.-09:46
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daveshahThat would make sense09:49
daveshahIt might be to do with IOLOGIC (input registers etc), needing to be routed through09:50
pepijndevosIIIINteresting... The IOB is connected to Q6, but a logic tile only has Q0-Q5 so my normal loop just doesn't make the right pip09:50
daveshahAt a guess, non-logic interconnect tiles have the extra Q6-709:51
daveshahI wouldn't be surprised if things like BRAM needed those extra signals too09:51
pepijndevosProbably. But it also means the muxes just have different options at these locations. So I need to go back and figure that out.09:52
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ZirconiumXCan somebody poke Clifford? I sent him an email 4 days ago and I'm unsure if he got it11:05
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* pepijndevos pokes11:11
ZirconiumXThanks Pepijn11:13
pepijndevosAlthough 4 days seems... not that much11:14
pepijndevosMaybe he'll see my poke in 4 days ;)11:15
ZirconiumXSure, but email is rather opaque for this :P11:15
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promachDo anyone have pcf examples for tinyfpga similar to ?11:53
tpbTitle: icebreaker-examples/icebreaker.pcf at master · icebreaker-fpga/icebreaker-examples · GitHub (at
tpbTitle: TinyFPGA-BX/pins.pcf at master · tinyfpga/TinyFPGA-BX · GitHub (at
promachthanks daveshah11:56
promachERROR: package does not have a pin named 'B2' (on line 94)   ???12:01
tpbTitle: TinyFPGA-BX/pins.pcf at master · tinyfpga/TinyFPGA-BX · GitHub (at
daveshahAre you passing --package to nextpnr12:02
promachwhat do you mean ? I am using GUI12:02
daveshahAre you choosing the right package?12:02
promachdaveshah is it bg121 ?12:05
daveshahNo, I think it is cm8112:05
promachcm81 or cm81:4k    ?12:06
promachfor tinyfpga BX12:06
promachdaveshah why is my json file is for hx1k ?12:08
tpbTitle: noc/spidergon.ys at master · promach/noc · GitHub (at
daveshahThe json file doesn't contain a device12:08
promachonce I open the JSON file, the GUI switch my choice from hx8k to hx1k12:09
daveshahI'm not sure why that is hapenning12:09
promachsynth_ice40 -flatten -top NoC -json spidergon.json12:10
promachis this command correctly ?12:10
daveshahIt sounds like the problem is on the iCE40 side12:10
promachdid I miss anything tinyfpga-specific parameters ?12:10
daveshahTry doing it on the command line nextpnr-ice40 --lp8k --json spidergon.json --package cm81 --gui12:11
promachyou forgot pin.pcf12:11
promachdaveshah usually which IO port is used for reset ?12:14
promachfor tinyfpga BX ?12:14
tpbTitle: TinyFPGA-BX/pins.pcf at master · tinyfpga/TinyFPGA-BX · GitHub (at
daveshahAny of the pins12:14
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promachdaveshah Warning: No clocks found in design12:57
daveshahSounds like you don't have any registered timing paths12:58
promachI do not understand. I have so many always @(posedge clk)12:58
daveshahAre there flip flops in the synthesis statistics?12:58
daveshahthey might be being optimised away12:58
promachdaveshah is the no clock warning because of ?12:58
tpbTitle: noc/spidergon.ys at master · promach/noc · GitHub (at
daveshahNo, because that doesn't remove any flops nor does it touch the JSON file that synth_ice40 previously created12:59
promachdaveshah then what causes the no clock warning ?12:59
daveshahare there the right number (roughly) of SB_DFFs in the log output of synth_ice4012:59
promachwhat log output ?13:00
daveshahit sounds a lot like your flipflops are being optimised out13:00
daveshahYosys' log output13:00
daveshahIt looks like your NoC module has only inputs13:00
daveshahThat means all the remaining logic will be optimised away13:01
promachand ?13:01
promachyou mean NoC.v13:02
daveshahthat is your top module, right?13:02
promachdaveshah so, there is nothing wrong for "Warning: No clocks found in design" ?13:03
promachand I do not need to fix anything ?13:03
daveshahWell, your design is empty13:03
promachempty ? what do you mean ?13:03
daveshahThere is no logic in your design13:03
promachwhat ?!13:04
daveshahIt's a circuit with only inputs13:04
promachso, the warning will go away once I add output ?13:04
daveshahYes, because then there will be some logic left13:05
daveshahso long as that output depends on some clocked logic13:05
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pepijndevosI'm still messed up with DFF naming16:38
pepijndevos_DFFE_PP_ is positive clock, positive reset, right?16:38
pepijndevosI mean... positive enable16:38
daveshahpositive clock, positive enable, no set/reset16:38
pepijndevos__DFFS_PN0_ is positive clock negative reset, reset to zero?16:39
daveshahyes, active low sync reset to zero16:39
pepijndevosand __DFFNSE_PN0 is... is it now the reset or the enablet that is negative?16:40
daveshahnegative enables aren't really well supported16:41
daveshah(dff2dffe doesn't map them, idk why there is even a primitive for them)16:41
pepijndevosSo once you have a reset, negative enable is just not a thing16:41
pepijndevosYea, that fixed it..16:42
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